IEICE Trans

Masao YANAGISAWA

Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy Jinghao YE Masao YANAGISAWA Youhua SHI
Publication: Publication Date: 2020/09/01 Vol. E103-A No. 9 pp. 1063-1070 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: FIR filter, area-power efficient, faithfully truncated adder,
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Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2020/07/01 Vol. E103-D No. 7 pp. 1618-1622 Type of Manuscript: Special Section LETTER (Special Section on Information and Communication System Security) Category: Network and System Security Keyword: hardware Trojan, gate-level netlist, Trojan feature, boundary nets, hardware design,
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Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone Yuri USAMI Kazuaki ISHIKAWA Toshinori TAKAYAMA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2019/08/01 Vol. E102-A No. 8 pp. 953-965 Type of Manuscript: PAPER Category: Intelligent Transport System Keyword: behavior recognition, smartphone, acceleration sensor, gyro sensor, bicycle,
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A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions Sae IWATA Kazuaki ISHIKAWA Toshinori TAKAYAMA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2019/06/01 Vol. E102-A No. 6 pp. 860-865 Type of Manuscript: LETTER Category: Intelligent Transport System Keyword: indoor/outdoor detection, sparse GPS, random forest classifier,
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A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests Tensei NISHIMURA Kazuaki ISHIKAWA Toshinori TAKAYAMA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2019/04/01 Vol. E102-A No. 4 pp. 641-653 Type of Manuscript: PAPER Category: Intelligent Transport System Keyword: cyclic-route generation, the route length constraint, multiple routes, Point-of-Interests,
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Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning Masaru OYA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2308-2319 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojans, gate-level netlist, steady state, signal transition, logic test,
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Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2320-2326 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojan, detection, gate-level netlist, multi-layer neural networks, machine learning,
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A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1045-1052 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: non-volatile memory, bit-write-reducing, error-correcting codes, clustering conditions, S-bit flip conditions, S-bound graph, cluster graph, relaxed REC code,
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A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element Saki TAJIMA Nozomu TOGAWA Masao YANAGISAWA Youhua SHI
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1025-1034 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: soft error, low-power, latch, C-element,
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Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs Ken HAYAMIZU Nozomu TOGAWA Masao YANAGISAWA Youhua SHI
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1014-1024 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: approximate computing, energy-efficient, adder, GeAr,
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Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams Ryota ISHIKAWA Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1002-1013 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: stochastic computing, stochastic number, duplicator, bit re-arrangement, re-convergence path,
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A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal Sae IWATA Tomoyuki NITTA Toshinori TAKAYAMA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/05/01 Vol. E101-A No. 5 pp. 831-843 Type of Manuscript: PAPER Category: Intelligent Transport System Keyword: sparse GPS positioning, clustering, stayed location estimation, positioning accuracy, effective radius,
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A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2911-2924 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, multiple-bitwidth, distributed-register architecture, operation chaining, interconnection delay, floorplan,
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Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2857-2868 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojan, gate-level netlist, Trojan-net feature, random forest, machine learning,
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A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions Siya BAO Tomoyuki NITTA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/11/01 Vol. E100-A No. 11 pp. 2439-2450 Type of Manuscript: PAPER Category: Intelligent Transport System Keyword: pedestrian, lighting, landmark, road width, turning point, anxiety, safety, comprehensiveness,
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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1439-1451 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, delay variation, body biasing, interconnection delay, floorplan,
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A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1427-1438 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: hardware Trojan, gate-level netlist, machine learning, support vector machine (SVM), neural network (NN),
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Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/04/01 Vol. E100-A No. 4 pp. 1015-1028 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: field-data extractor, multiplexer network, partitioning, rotator,
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A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2398-2411 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: non-volatile memory, bit-write-reducing, error-correcting codes, clustering conditions, S-bit flip conditions, S-bound graph, cluster graph, REC code,
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A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices Ryosuke KITAYAMA Takashi TAKENAKA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2348-2362 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: IoT, power analyzer, noise reduction, signal-averaging method, scalable measurement,
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Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching Masaru OYA Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2335-2347 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojans, gate-level netlist, a quantitative criterion, pattern matching, design phase,
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A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1278-1293 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, process variation, interconnection delay, distributed-register architecture, scenario,
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Bi-Partitioning Based Multiplexer Network for Field-Data Extractors Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1410-1414 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: multiplexer network, partitioning, field-data extractor,
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Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1294-1310 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: interconnection delay, clock skew, high-level synthesis (HLS), FPGA, floorplan,
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Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2484-2493 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: non-volatile memory, maximum-writing bits, error-correcting codes, Doughnut code, code expansion,
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A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists Masaru OYA Youhua SHI Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Satoshi GOTO Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2537-2546 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: hardware Trojans, golden-IC free, classification, identification, gate-level netlist,
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Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures Huiqian JIANG Mika FUJISHIRO Hirokazu KODERA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2547-2555 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: Camellia, side-channel attack, scan-based attack, design-for-test, scan chain, scan signature,
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ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory Masashi TAWADA Shinji KIMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2494-2504 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: non-volatile memory, bit-write reduction, energy reduction, write-reduction code, error-correcting code,
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An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1376-1391 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, energy-optimization, interconnection delay, multiple clock domains,
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A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1366-1375 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, RDR architecture, interconnection delay, operation chaining, floorplan,
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A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Shin-ya ABE Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1392-1405 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis (HLS), FPGA, floorplan, interconnection delay, MUX,
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An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead Shinnosuke YOSHIDA Youhua SHI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1406-1418 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: timing-error prediction, robust design, delay variation, overclocking,
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Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures Mika FUJISHIRO Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2434-2442 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: LED, light encryption device, side-channel attacks, scan chain, scan-based attack,
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Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures Mika FUJISHIRO Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/07/01 Vol. E97-A No. 7 pp. 1444-1451 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: Trivium, side-channel attacks, scan chain, scan-based attack,
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Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2597-2611 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, interconnection delay, energy-optimization, dynamic multiple supply voltages,
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A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1283-1292 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: cache simulation, optimaize cache memory, multicore cache,
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A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/01/01 Vol. E96-A No. 1 pp. 312-321 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, RDR, thermal-aware, hot spots, interconnect delays,
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Scan-Based Attack on AES through Round Registers and Its Countermeasure Youhua SHI Nozomu TOGAWA Masao YANAGISAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2338-2346 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: scan-based side channel attack, crypto implementation, security, testability,
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A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores Seungju LEE Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/09/01 Vol. E95-A No. 9 pp. 1538-1549 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: network-on-chip (NoC), hybrid NoC algorithm, hierarchical NoC, busmesh NoC (BMNoC),
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Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2482-2489 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power supply noise, power distribution network, signal integrity, circuit simulation,
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Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/04/01 Vol. E94-A No. 4 pp. 1082-1090 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: power supply noise, power distribution networks, signal integrity, circuit simulation,
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Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures Ryuta NARA Kei SATOH Masao YANAGISAWA Tatsuo OHTSUKI Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2481-2489 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: scan-based side-channel attack, scan path, testability, cryptosystem, RSA, security,
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A Two-Level Cache Design Space Exploration System for Embedded Applications Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3238-3247 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: two-level cache, L1/L2, cache optimization, design space exploration, cache simulation, embedded system,
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X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3119-3127 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: scan test, test data compression, X-masking,
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A Scan-Based Attack Based on Discriminators for AES Cryptosystems Ryuta NARA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3229-3237 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: scan-based attack, side-channel attack, scan chain, testability, security, cryptography, AES,
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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures Akira OHCHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3169-3179 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, floorplan, distributed-register architecture, generalized distributed-register architecture, local register, local controller,
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Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2ⁿ) Kazuyuki TANIMURA Ryuta NARA Shunitsu KOHARA Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 pp. 2304-2317 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: elliptic curve cryptography, dual-radix, modular multiplication, Montgomery multiplication, scalability, unified,
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An L1 Cache Design Space Exploration System for Embedded Applications Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-A No. 6 pp. 1442-1453 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: cache, cache optimization, design space exploration, cache simulation, embedded system,
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A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3514-3523 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: scan test, test data compression, X-masking,
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A Secure Test Technique for Pipelined Advanced Encryption Standard Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 776-780 Type of Manuscript: Special Section LETTER (Special Section on Test and Verification of VLSIs) Category: Keyword: scan test, security, test quality,
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Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains Youhua SHI Nozomu TOGAWA Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 996-1004 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: test data compression, test channels, scan test,
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A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 243-249 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: System LSIs and Microprocessors Keyword: elliptic curve cryptosystem, Montgmery multiplier, public-key cryptosystem, LSI design,
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A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1340-1349 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Programmable Logic, VLSI, CAD and Layout Keyword: processor synthesis, instruction set synthesis, packed SIMD-type functional unit, packed SIMD-type instruction, hardware/software cosynthesis,
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Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis Hideki KAWAZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 876-884 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: processor synthesis, packed SIMD type operation, hardware/software partitioning, hardware/software cosynthesis, sub-operation parallelism,
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A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction Youhua SHI Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3208-3215 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: test data compression, scan chain reconfiguration, run-length coding, scan-in power consumption,
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A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs Youhua SHI Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3193-3199 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: test data compression, test slice, multiple scan chain, ATE,
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High-Level Power Optimization Based on Thread Partitioning Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3075-3082 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: high-level synthesis, low power, thread partitioning, gated clocks,
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FPGA-Based Reconfigurable Adaptive FEC Kazunori SHIMIZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3036-3046 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: dynamic reconfigurable system, adaptive FEC, FPGA, Reed Solomon codes,
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A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/04/01 Vol. E87-A No. 4 pp. 830-836 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: hardware/software cosynthesis, processor synthesis, heterogeneous datapaths and heterogeneous registers,
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A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions Nozomu TOGAWA Kyosuke KASAHARA Yuichiro MIYAOKA Jinku CHOI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3099-3109 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation Accelerator Keyword: retargetable simulator, DSP processor, packed SIMD type instruction, hardware/software cosynthesis, processor synthesis,
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A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3218-3224 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Design Methodology Keyword: processor synthesis, packed SIMD type instruction, hardware/software partitioning, hardware/software cosynthesis, DSP processor,
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A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation Youhua SHI Zhe ZHANG Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3056-3062 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: reseeding, LFSR, BIST, test pattern generation,
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A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories Nozomu TOGAWA Takao TOTSUKA Tatsuhiko WAKUI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/05/01 Vol. E86-A No. 5 pp. 1082-1092 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: content addressable memory, functional memory, micro processor core, hardware/software cosynthesis, hardware/software partitioning,
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A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2655-2666 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High Level Synthesis Keyword: high-level synthesis, energy optimization, area/time constraints,
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An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation Jinku CHOI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2603-2611 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: motion estimation, block-matching, algorithm, architecture, VHDL,
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High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 827-834 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: high-level synthesis, power estimation, gated clock, switching activity, sequential circuit,
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A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files Nozomu TOGAWA Takashi SAKURAI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2802-2807 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Hardware/Software Codesign Keyword: hardware/software cosynthesis, hardware/software partitioning, digital signal processor (DSP), register file, hardware unit,
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Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores Nozomu TOGAWA Yoshiharu KATAOKA Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2639-2647 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Hardware/Software Codesign Keyword: area estimation, delay estimation, hardware/software cosynthesis, digital signal processor (DSP), microprocessor,
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An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares Nozomu TOGAWA Masayuki IENAGA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/05/01 Vol. E84-A No. 5 pp. 1166-1176 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: high-level synthesis, control-based hardware, area/time optimization, scheduling, resource allocation,
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CAM Processor Synthesis Based on Behavioral Descriptions Nozomu TOGAWA Tatsuhiko WAKUI Tatsuhiko YODEN Makoto TERAJIMA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2464-2473 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Co-design and High-level Synthesis Keyword: content addressable memory, functional memory, behavioral synthesis, behavioral description, high-level synthesis,
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A High Performance Embedded Wavelet Video Coder Tingrong ZHAO Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/25 Vol. E83-A No. 6 pp. 979-986 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99)) Category: Keyword: wavelet transform, zerotree, embedded coding, multiresolution, motion estimation, video coding,
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A Hardware/Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/03/25 Vol. E83-A No. 3 pp. 442-451 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: hardware/software cosynthesis, processor core, digital signal processing, two types of register files,
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A Hardware/Software Cosynthesis System for Digital Signal Processor Cores Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2325-2337 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware/software cosynthesis, hardware/software partitioning, processor core, digital signal processing,
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EDITORS' ADDRESS Suguru ARIMOTO Masao YANAGISAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/05/25 Vol. E82-A No. 5 pp. 711-712 Type of Manuscript: EDITORS' ADDRESS Category: Keyword:
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A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs Nozomu TOGAWA Koji ARA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/03/25 Vol. E82-A No. 3 pp. 473-482 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: technology mapping, logic-block, lookup table, logic depth,
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A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration Nozomu TOGAWA Takafumi HISAKI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2563-2575 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-level Synthesis Keyword: data-flow oriented process, high-level synthesis, data-flow graph enumeration, scheduling, resource binding,
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A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/06/25 Vol. E81-A No. 6 pp. 1231-1241 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: scheduling, resource binding, high-level synthesis, data-flow graph, gradual time-frame reduction,
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An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications Nozomu TOGAWA Kayoko HAGI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-A No. 5 pp. 873-884 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: FPGA, engineering change, layout reconfiguration, placement and routing,
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