Masao SATO


Fast Scheduling and Allocation Algorithms for Entropy CODEC
Katsuharu SUZUKI Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 982-992
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High Level Synthesis
Keyword: 
entropy CODECschedulingallocationcontrol-flow graph
 Summary | Full Text:PDF

A performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1795-1806
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAtransport processinglayout designplacement and routingperformance optimizationcircuit delay
 Summary | Full Text:PDF

A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 494-505
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGAmulti-FPGA systemcircuit partitioningpath delaylogic-block replication
 Summary | Full Text:PDF

Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout
Nozumu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2140-2150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAtransport processinglayout designplacement and routing network flow
 Summary | Full Text:PDF

A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 321-329
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGAtechnology mappinglayoutpath delayperformance optimization
 Summary | Full Text:PDF

A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1765-1776
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAcircuit partitioninglogic-block replicationnetwork flow
 Summary | Full Text:PDF

A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size
Shinsuke OHNO Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1755-1764
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Content Addressable Memory (CAM)parallel fault simulationbit reusing strategypipeline propagationhardware engine
 Summary | Full Text:PDF

Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2028-2038
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAlook up tabletechnology mappinglayout designplacementglobal routing
 Summary | Full Text:PDF

Optimal Constraint Graph Generation Algorithm for Layout Compaction Using Enhanced Plane-Sweep Method
Toru AWASHIMA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4  pp. 507-512
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computer aided designLSI design technologylayout designcompactionplane-sweep method
 Summary | Full Text:PDF

A VLSI Geometrical Design Rule Verification Accelerated by CAM-Based Hardware Engine
Tetsuro TAKIZAWA Kazuto KUBOTA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/10/25
Vol. E74-A  No. 10  pp. 3072-3077
Type of Manuscript:  Special Section PAPER (Special Issue on JTC-CSCC '90)
Category: VLSI Design Technology
Keyword: 
 Summary | Full Text:PDF