Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-ANo. 12pp. 2576-2586 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: heterogeneous multicore processor, FPGA, Multimedia processing, High-performance-computing,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-DNo. 8pp. 1632-1644 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: FPGA, reconfigurable LSI, self-timed circuit, asynchronous circuit,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-DNo. 2pp. 354-363 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: memory allocation, partitioning, reconfigurable processors,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-ANo. 1pp. 342-351 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: memory allocation, parallel data access, addressing,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-ANo. 12pp. 2570-2580 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: heterogeneous multi-core processor, task-allocation, system-on-chip,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-ANo. 12pp. 3596-3606 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, low power, interconnection network, genetic algorithm,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-CNo. 4pp. 479-486 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: stereo vision, scheduling, allocation,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-CNo. 11pp. 1551-1558 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: automatic synthesis, scheduling, module selection, data-path design, optimization,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-ANo. 12pp. 3298-3305 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: reconfigurable processor, FPGA, multiple-supply-voltage scheme,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-ANo. 12pp. 3516-3522 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: stereo vision, FPGA, scheduling, allocation,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-DNo. 7pp. 1486-1491 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Digital Circuits and Computer Arithmetic Keyword: stereo vision, SAD (sum of absolute differences), memory allocation, logic-in-memory architecture,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-CNo. 11pp. 1897-1902 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: reconfigurable architecture, FPGA, bit-serial architecture,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-CNo. 9pp. 1722-1729 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Processors Keyword: hierarchical collision detection, area-time product minimization, CAM, path planning,