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Masanori HARIYAMA

Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2658-2669 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: heterogeneous multicore, FPGA, custom accelerators, reconfigurable architecture,
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Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2576-2586 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: heterogeneous multicore processor, FPGA, Multimedia processing, High-performance-computing,
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Architecture of an Asynchronous FPGA for Handshake-Component-Based Design Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1632-1644 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: FPGA, reconfigurable LSI, self-timed circuit, asynchronous circuit,
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Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation Yoshitaka HIRAMATSU Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Toru NOJIRI Kunio UCHIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/12/01 Vol. E95-C No. 12 pp. 1872-1882 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: block matching, heterogeneous multi-core, dynamically reconfigurable processor, data transfer, accelerator,
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Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates Zhengfan XIA Shota ISHIHARA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/08/01 Vol. E95-C No. 8 pp. 1434-1443 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: asynchronous pipeline, dual-rail, critical datapath,
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Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors Hasitha Muthumala WAIDYASOORIYA Yosuke OHBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 354-363 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: memory allocation, partitioning, reconfigurable processors,
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Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/10/01 Vol. E94-C No. 10 pp. 1669-1679 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: mixed synchronous/asynchronous design, reconfigurable VLSI, four-phase dual-rail encoding, self-timed architecture, GALS (Globally Asynchronous Locally Synchronous),
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Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 pp. 342-351 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: memory allocation, parallel data access, addressing,
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Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation Hasitha Muthumala WAIDYASOORIYA Daisuke OKUMURA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2570-2580 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: heterogeneous multi-core processor, task-allocation, system-on-chip,
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An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture Shota ISHIHARA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/08/01 Vol. E93-C No. 8 pp. 1338-1348 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: reconfigurable VLSI, field-programmable VLSI, LEDR (Level-Encoded Dual-Rail) encoding, 4-phase dual-rail encoding, self-timed architecture,
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A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals Shota ISHIHARA Noriaki IDOBATA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2134-2144 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Application of Multiple-Valued VLSI Keyword: dynamically programmable gate array, multi-context switch, logic-in-memory circuit, multiple-valued threshold logic, nonvolatile storage, non-destructive operation,
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Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 pp. 539-549 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: DPGA, multi-context, asynchronous FPGA,
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Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3596-3606 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, low power, interconnection network, genetic algorithm,
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Memory Allocation for Multi-Resolution Image Processing Yasuhiro KOBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/10/01 Vol. E91-D No. 10 pp. 2386-2397 Type of Manuscript: PAPER Category: VLSI Systems Keyword: high-level synthesis, interconnection-aware architecture, stereo vision,
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Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture Masanori HARIYAMA Shota ISHIHARA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 pp. 1419-1426 Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation) Category: Keyword: FPGAs, reconfigurable VLSIs, asynchronous architecture, LEDR (Level-Encoded Dual-Rail) encoding,
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Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling Masanori HARIYAMA Naoto YOKOYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 479-486 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: stereo vision, scheduling, allocation,
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Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment Hasitha Muthumala WAIDYASOORIYA Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 517-525 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: dynamically-programmable gate array, multi-context FPGA, configuration data redundancy,
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A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates Masanori HARIYAMA Sho OGATA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1655-1661 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: time-multiplexed FPGA, dynamically reconfigurable architecture, DPGA, bit-serial architecture,
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Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification Masanori HARIYAMA Shigeo YAMADERA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1551-1558 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: automatic synthesis, scheduling, module selection, data-path design, optimization,
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Low-Power Field-Programmable VLSI Using Multiple Supply Voltages Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3298-3305 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: reconfigurable processor, FPGA, multiple-supply-voltage scheme,
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FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture Masanori HARIYAMA Yasuhiro KOBAYASHI Haruka SASAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3516-3522 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: stereo vision, FPGA, scheduling, allocation,
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Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access Masanori HARIYAMA Haruka SASAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1486-1491 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Digital Circuits and Computer Arithmetic Keyword: stereo vision, SAD (sum of absolute differences), memory allocation, logic-in-memory architecture,
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Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1897-1902 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: reconfigurable architecture, FPGA, bit-serial architecture,
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Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme Masanori HARIYAMA Seunghwan LEE Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/03/01 Vol. E84-C No. 3 pp. 382-389 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: motion stereo, memory allocation, functional-unit allocation,
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An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/12/25 Vol. E83-D No. 12 pp. 2122-2130 Type of Manuscript: PAPER Category: Image Processing, Image Pattern Recognition Keyword: motion stereo, FPGA-based processor, memory allocation, functional unit allocation,
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Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory Masanori HARIYAMA Kazuhiro SASAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1722-1729 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Processors Keyword: hierarchical collision detection, area-time product minimization, CAM, path planning,
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A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/11/25 Vol. E80-C No. 11 pp. 1491-1498 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 3-D instrumentation, epipolar constraint, block matching algorithm, special-purpose VLSI processor, memory interleaving,
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Design of a CAM-Based Collision Detection VLSI Processor for Robotics Masanori HARIYAMA Michitaka KANEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/25 Vol. E77-C No. 7 pp. 1108-1115 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: special-purpose VLSI, content-addressable memory (CAM), rectangular solid representation, CORDIC algorithms,
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A Collision Detection Processor for Intelligent Vehicles Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/25 Vol. E76-C No. 12 pp. 1804-1811 Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: special-purpose VLSI, content-addressable memory, rectangular solid representation,
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