Masami SUETAKE


A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential
Dondee NAVARRO Takeshi MIZOGUCHI Masami SUETAKE Kazuya HISAMITSU Hiroaki UENO Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 1079-1086
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
pinch-off regionchannel-length modulationoverlap capacitancesurface-potential-based modelingcircuit simulation
 Summary | Full Text:PDF

Worst/Best Device and Circuit Performances for MOSFETs Determined from Process Fluctuations
Odin PRIGGE Masami SUETAKE Mitiko MIURA-MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6  pp. 997-1002
Type of Manuscript:  Special Section PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
MOSFETperformance distribution 2σanalytical model
 Summary | Full Text:PDF