Masami NAKAJIMA


Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture
Toru SHIMIZU Masami NAKAJIMA Masahiro KAINAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1512-1518
Type of Manuscript:  INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
massively parallel processorSIMDfine-grained ALUwideband bus
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Design of Highly Parallel Linear Digital System for ULSI Processors
Masami NAKAJIMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1119-1125
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
locally computable combinational circuitslinear digital circuitscode assignmentunary operations
 Summary | Full Text:PDF