Masaki TSUKUDE


A Long Data Retention SOI DRAM with the Body Refresh Function
Shigeki TOMISHIMA Fukashi MORISHITA Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 899-904
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Structure Devices
Keyword: 
memorySOI-DRAMbody regionrefreshdata retention
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SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories
Shigehiro KUGE Fukashi MORISHITA Takahiro TSURUDA Shigeki TOMISHIMA Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 997-1002
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
Keyword: 
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A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs
Shigeki TOMISHIMA Shigehiro KUGE Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 808-811
Type of Manuscript:  Special Section LETTER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memorytriple metalsource linelayout
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A Line-Mode Test with Data Register for ULSI Memory Architecture
Tsukasa OOISHI Masaki TSUKUDE Kazutani ARIMOTO Yoshio MATSUDA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1595-1603
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
line-mode testdata inversion registermain-sub I/O line architecture
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A New Array Architecture for 16 Mb DRAMs with Special Page Mode
Masaki TSUKUDE Tsukasa OISHI Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10  pp. 1267-1274
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
array architecturedynamic memoryhigh speed accesswide operating marginlow power dissipation
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