IEICE Trans

Masaki NAKANISHI

A Fast Quantum Computer Simulator Based on Register Reordering Masaki NAKANISHI Miki MATSUYAMA Yumi YOKOO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/02/01 Vol. E99-D No. 2 pp. 332-340 Type of Manuscript: PAPER Category: Computer System Keyword: quantum computer simulator, hardware implementation, register reordering,
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Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication Marcos VILLAGRA Masaki NAKANISHI Shigeru YAMASHITA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/01/01 Vol. E96-D No. 1 pp. 1-8 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: multiparty communication complexity, quantum computation, quantum nondeterminism, tensor rank,
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Quantum Walks on the Line with Phase Parameters Marcos VILLAGRA Masaki NAKANISHI Shigeru YAMASHITA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/03/01 Vol. E95-D No. 3 pp. 722-730 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science – Mathematical Foundations and Applications of Computer Science and Algorithms –) Category: Keyword: quantum computation, random walks, quantum walks, asymptotic approximation,
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Multi-Party Quantum Communication Complexity with Routed Messages Seiichiro TANI Masaki NAKANISHI Shigeru YAMASHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/02/01 Vol. E92-D No. 2 pp. 191-199 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science) Category: Keyword: quantum communication complexity, network topology, distributed computing,
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Robust Quantum Algorithms Computing OR with ε-Biased Oracles Tomoya SUZUKI Shigeru YAMASHITA Masaki NAKANISHI Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/02/01 Vol. E90-D No. 2 pp. 395-402 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science) Category: Quantum Computing Keyword: quantum computing, biased oracle, phase estimation,
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An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs Mitsuru TOMONO Masaki NAKANISHI Shigeru YAMASHITA Kazuo NAKAJIMA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3416-3426 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: algorithm, online placement, partially reconfigurable FPGAs, reconfigurable computing,
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Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3427-3434 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: HDL, high-level synthesis, bit-length optimization, non-linear programming,
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Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition Masaki NAKANISHI Kiyoharu HAMAGUCHI Toshinobu KASHIWABARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1120-1127 Type of Manuscript: PAPER Category: Computation and Computational Models Keyword: quantum pushdown automata, quantum computation model, context-free-language,
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Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3184-3191 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic and High Level Synthesis Keyword: HDL, high-level synthesis, parallelizing compiler, bit length,
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Look Up Table Compaction Based on Folding of Logic Functions Shinji KIMURA Atsushi ISHII Takashi HORIYAMA Masaki NAKANISHI Hirotsugu KAJIHARA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2701-2707 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: field programmable gate array (FPGA), LUT architecture, reconfigurable logic,
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On the Power of Non-deterministic Quantum Finite Automata Masaki NAKANISHI Takao INDOH Kiyoharu HAMAGUCHI Toshinobu KASHIWABARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/02/01 Vol. E85-D No. 2 pp. 327-332 Type of Manuscript: Special Section PAPER (Special Issue on Selected Papers from LA Symposium) Category: Keyword: quantum computation, quantum finite automaton, non-deterministic finite automaton, regular language,
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An Exponential Lower Bound on the Size of a Binary Moment Diagram Representing Integer Division Masaki NAKANISHI Kiyoharu HAMAGUCHI Toshinobu KASHIWABARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/05/25 Vol. E82-A No. 5 pp. 756-766 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: binary moment diagram, division, lower bound,
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