Masakazu KAKUMU


Design Methodology of Deep Submicron CMOS Devices for 1 V Operation
Hisato OYAMATSU Masaaki KINUGAWA Masakazu KAKUMU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1720-1725
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
low voltagelow power dissipationthreshold voltageCMOS
 Summary | Full Text:PDF(464.6KB)

High-Density Full-CMOS SRAM Cell Technology with a Deep Sub-Micron Spacing between nMOS and pMOSFET
Fumitomo MATSUOKA Kazunari ISHIMARU Hiroshi GOJOHBORI Hidetoshi KOIKE Yukari UNNO Manabu SAI Toshiyuki KONDO Ryuji ICHIKAWA Masakazu KAKUMU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1385-1394
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: General Technology
Keyword: 
full-CMOS SRAM cellshallow trench isolationdual gate CMOS
 Summary | Full Text:PDF(1.1MB)

Process and Device Technologies of CMOS Devices for Low-Voltage Operation
Masakazu KAKUMU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 672-680
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits)
Category: 
Keyword: 
CMOSSOISIMOXMOSFETlow-voltagelow-temperaturethreshold voltage high-speedpower-supply voltagesubthreshold currentcircuit performancepower dissipation
 Summary | Full Text:PDF(687.8KB)