Masahiro SEKIYA

Design of a Sub-1. 5 V, 20 MHz, 0. 1% MOS Current-Mode Sample-and-Hold Circuit
Yasuhiro SUGIMOTO Masahiro SEKIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A  No. 2  pp. 258-260
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
low voltage, high speed, high accuracy, MOS analog circuit, sample-and-hold circuit, 
 Summary | Full Text:PDF
A Study of the Signal-to-Noise Ratio of a High-Speed Current-Mode CMOS Sample-and-Hold Circuit
Yasuhiro SUGIMOTO Masahiro SEKIYA Tetsuya IIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1986-1993
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
signal-to-noise ratio, noise analysis, sample-and-hold circuit, current-mode circuit, MOS analog circuit, 
 Summary | Full Text:PDF