Masahiro KAINAGA


Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture
Toru SHIMIZU Masami NAKAJIMA Masahiro KAINAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1512-1518
Type of Manuscript:  INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
massively parallel processorSIMDfine-grained ALUwideband bus
 Summary | Full Text:PDF

Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH
Hideo MAEJIMA Masahiro KAINAGA Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1539-1545
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
RISCarchitecturelow powerhigh speedmicroprocessor
 Summary | Full Text:PDF