Masahiro IWAMURA


Design of the Basic Cell and Metallized RAM for 0.5 µm CMOS Gate Array
Yoji NISHIO Hideo HARA Masahiro IWAMURA Yasuo KAMINAGA Katsunori KOIKE Kosaku HIROSE Takayuki NOTO Satoshi OGUCHI Yoshihiko YAMAMOTO Takeshi ONO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Vol. E78-C  No. 9  pp. 1255-1262
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
gate arraybasic cellcompiled RAMmetallized RAM
 Summary | Full Text:PDF(799.7KB)

BiCMOS Circuit Techniques for 3.3 V Microprocessors
Fumio MURABAYASHI Tatsumi YAMAUCHI Masahiro IWAMURA Takashi HOTTA Tetsuo NAKANO Yutaka KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 695-700
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits)
Category: 
Keyword: 
low voltageBiCMOScommon-base sense circuitpass logic addercomparator with wired-OR
 Summary | Full Text:PDF(534.6KB)