IEICE Trans

Masahiro FUKUI

A New Algorithm for Reducing Components of a Gaussian Mixture Model Naoya YOKOYAMA Daiki AZUMA Shuji TSUKIYAMA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2425-2434 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: Gaussian mixture model, reduction of components, normalized integral square error, sensitivity, statistical method,
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FOREWORD Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1277-1277 Type of Manuscript: FOREWORD Category: Keyword:
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FOREWORD Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2483-2483 Type of Manuscript: FOREWORD Category: Keyword:
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Adaptive Spectral Masking of AVQ Coding and Sparseness Detection for ITU-T G.711.1 Annex D and G.722 Annex B Standards Masahiro FUKUI Shigeaki SASAKI Yusuke HIWASAKI Kimitaka TSUTSUMI Sachiko KURIHARA Hitoshi OHMURO Yoichi HANEDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/05/01 Vol. E97-D No. 5 pp. 1264-1272 Type of Manuscript: PAPER Category: Speech and Hearing Keyword: speech and audio coding, standardization, ITU-T G.711.1 Annex D, ITU-T G.722 Annex B, super-wideband (SWB) extension, algebraic vector quantization (AVQ),
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Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path Ittetsu TANIGUCHI Kohei AOKI Hiroyuki TOMIYAMA Praveen RAGHAVAN Francky CATTHOOR Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/02/01 Vol. E97-A No. 2 pp. 606-615 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: design space exploration, architecture exploration, very long instruction-set word (VLIW) processor, genetic algorithm (GA),
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A New Delay Distribution Model with a Half Triangular Distribution for Statistical Static Timing Analysis Shuji TSUKIYAMA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2542-2552 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: distribution model, half triangular distribution, long-term degradations, statistical maximum, mixture model, non-Gaussian distr ibution, statistical static timing analysis,
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Network Topology and Battery Size Exploration for Decentralized Energy Network with MIP Base Power Flow Optimization Ittetsu TANIGUCHI Kazutoshi SAKAKIBARA Shinya KATO Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/07/01 Vol. E96-A No. 7 pp. 1617-1624 Type of Manuscript: PAPER Category: General Fundamentals and Boundaries Keyword: design optimization, mixed integer programming (MIP), combinatorial optimization problem, smart grid,
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A Statistical Maximum Algorithm for Gaussian Mixture Models Considering the Cumulative Distribution Function Curve Shuji TSUKIYAMA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2528-2536 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical maximum, Gaussian mixture model, cumulative distribution function curve, statistical static timing analysis,
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An Efficient Algorithm for RTL Power Macro-Modeling and Library Building Masaaki OHTSUKI Masato KAWAI Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 pp. 500-507 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: power macro model, power consumption estimation, power model library, LUT,
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A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop Yoshiyuki KAWAKAMI Makoto TERAO Masahiro FUKUI Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3423-3430 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power grid optimization, timing violation, critical path, process variation, IR drop,
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A Power Modeling and Optimization Scheme for Future Ultra Small Size Electric Systems Masahiro FUKUI Sayaka IWAKOSHI Tatsuya KOYAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1900-1908 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Low-Power and High-Performance VLSI Circuit Technology Keyword: system operated by battery, low power, power dissipation model, battery model,
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An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays Shuji TSUKIYAMA Masakazu TANAKA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2746-2754 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: static timing analysis, statistical approach, correlation, normal distribution, CMOS combinatorial circuits,
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WSSA: A High Performance Simulated Annealing and Its Application to Transistor Placement Shunji SAIKA Masahiro FUKUI Masahiko TOYONAGA Toshiro AKINO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2584-2591 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Synthesis Keyword: simulated annealing, temperature scheduling, phase transition, placement optimization, cell synthesis,
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Layout Abstraction and Technology Retargeting for Leaf Cells Masahiro FUKUI Noriko SHINOMIYA Syunji SAIKA Toshiro AKINO Shigeo KUNINOBU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2492-2500 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Optimization Keyword: technology retargeting, layout abstraction, layout synthesis, cell synthesis,
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Design Optimization by Using Flexible Pipelined Modules Masahiro FUKUI Masakazu TANAKA Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2521-2528 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Optimization Keyword: pipeline, design tuning, module generation,
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A Pin Assignment and Global Routing Algorithm for Floorplanning Takahiro SHIOHARA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/08/25 Vol. E81-A No. 8 pp. 1725-1732 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: floorplan, pin assignment, global route, maximum flow algorithm,
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A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells Shunji SAIKA Masahiro FUKUI Noriko SHINOMIYA Toshiro AKINO Shigeo KUNINOBU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 pp. 1883-1891 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: cell layout, cell synthesis, transistor placement, two-dimensional placement,
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