IEICE Trans

Masahiro FUJITA

Signal Selection Methods for Debugging Gate-Level Sequential Circuits Yusuke KIMURA Amir Masoud GHAREHBAGHI Masahiro FUJITA
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 pp. 1770-1780 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic debugging, engineering change order (ECO), sequential circuits, reachability analysis,
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C Description Reconstruction Method from a Revised Netlist for ECO Support Yusuke KIMURA Amir Masoud GHAREHBAGHI Masahiro FUJITA
Publication: Publication Date: 2018/04/01 Vol. E101-A No. 4 pp. 685-696 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: C reconstruction, ECO, CEGIS, program synthesis,
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Fast and Efficient Signature-Based Sub-Circuit Matching Amir Masoud GHAREHBAGHI Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1355-1365 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: circuit matching, signature-based matching, similarity detection,
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An Energy-Efficient Patchable Accelerator and Its Design Methods Hiroaki YOSHIDA Masayuki WAKIZAKA Shigeru YAMASHITA Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2507-2517 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: engineering change, high-level synthesis, energy efficiency,
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Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model Amir Masoud GHAREHBAGHI Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/04/01 Vol. E97-D No. 4 pp. 852-863 Type of Manuscript: PAPER Category: Dependable Computing Keyword: design error diagnosis, design error correction, micro architecture debugging, formal verification, processors,
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Transaction Ordering in Network-on-Chips for Post-Silicon Validation Amir Masoud GHAREHBAGHI Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2309-2318 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: post-silicon validation, transaction ordering, network-on-a-chip (NoC), system-on-a-chip (SoC),
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An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging Yeonbok LEE Takeshi MATSUMOTO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/07/01 Vol. E94-A No. 7 pp. 1519-1529 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: post-silicon debugging, high-level design, I/O sequence mapping,
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Multi-Level Bounded Model Checking with Symbolic Counterexamples Tasuku NISHIHARA Takeshi MATSUMOTO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/02/01 Vol. E94-A No. 2 pp. 696-705 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: formal verification, bounded model checking, finite state machine with datapath, symbolic simulation,
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Interconnect-Aware Pipeline Synthesis for Array-Based Architectures Shanghua GAO Hiroaki YOSHIDA Kenshu SETO Satoshi KOMATSU Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-A No. 6 pp. 1464-1475 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: software pipelining, interconnect delay, high level synthesis, scheduling, performance,
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A Unified Framework for Equivalence Verification of Datapath Oriented Applications Bijan ALIZADEH Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/05/01 Vol. E92-D No. 5 pp. 985-994 Type of Manuscript: Special Section PAPER (Special Section on Formal Approach) Category: Hardware Verification Keyword: equivalence verification, canonical form, RTL model, gate-level implementation, decision diagram,
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Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath Tasuku NISHIHARA Takeshi MATSUMOTO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/05/01 Vol. E92-D No. 5 pp. 972-984 Type of Manuscript: Special Section PAPER (Special Section on Formal Approach) Category: Hardware Verification Keyword: high-level synthesis, behavioral synthesis, formal verification, equivalence checking,
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The AMS Extension to System Level Design Language--SpecC Yu LIU Satoshi KOMATSU Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3397-3407 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: system level design language, AMS, SpecC, continuous behavior,
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Synchronization Verification in System-Level Design with ILP Solvers Thanyapat SAKUNKONCHAK Satoshi KOMATSU Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3387-3396 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: formal verification, SpecC language, event synchronization, Boolean programs, automatic abstraction refinement, assertion-based verification,
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Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment Yu LIU Satoshi KOMATSU Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 1018-1026 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: AMS extension, system level design language, timed/untimed, mixed-signal, synchronization, SpecC language,
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Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications Satoshi KOMATSU Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3282-3289 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: bus encoding, ECC/EDC, low power, reliability,
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An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences Takeshi MATSUMOTO Hiroshi SAITO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3315-3323 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: equivalence checking, C-based system level design, symbolic simulation, textual difference, program slicing,
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Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams Thanyapat SAKUNKONCHAK Satoshi KOMATSU Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3192-3199 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic and High Level Synthesis Keyword: SpecC language, event synchronization, difference decision diagrams (DDDs), Boolean programs, abstraction refinement,
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Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks Satoshi KOMATSU Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3001-3008 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power Optimization Keyword: low power encoding, address bus, signal transition, address locality,
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Network Resynthesis Algorithms for Delay Minimization Kuang-Chien CHEN Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 pp. 1102-1113 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: gate resynthesis, sum-to-one subsets, permissible functions, candidate cubes, tautology-checking,
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Enhanced Unique Sensitization for Efficient Test Generation Yusuke MATSUNAGA Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 pp. 1114-1120 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Test Keyword: computer hardware and disign, testing and verification,
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Timing Optimization of Multi-Level Networks Using Boolean Relations Yuji KUKIMOTO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/03/25 Vol. E76-A No. 3 pp. 362-369 Type of Manuscript: Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems) Category: Keyword: timing optimization, logic synthesis, logic optimization, Boolean relations, Boolean unification,
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Applications of Boolean Unification to Combinational Logic Synthesis Yuji KUKIMOTO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 pp. 1212-1219 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: Boolean unification, Boolean equations, logic synthesis, logic optimization, Boolean relations,
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Coupling of Memory Search and Mental Rotation by a Nonequilibrium Dynamics Neural Network Jun TANI Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/05/25 Vol. E75-A No. 5 pp. 578-585 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Dynamics--Adaptive, Learning and Neural Systems--) Category: Neural Systems Keyword: neural network, chaos, mental rotation,
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