Masahiko YOSHIMOTO


Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor
Shintaro IZUMI Takaaki OKANO Daichi MATSUNAGA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   
Publication Date: 2019/06/01
Vol. E102-B  No. 6  pp. 1088-1096
Type of Manuscript:  Special Section PAPER (Special Section on Healthcare, Medical Information and Communication Technology for Safe and Secure Society)
Category: 
Keyword: 
Burg's methodheart rate variabilityinstantaneous heart rate (IHR)microwave Doppler sensornon-contact
 Summary | Full Text:PDF(2.8MB)

Recent Progress of Biomedical Processor SoC for Wearable Healthcare Application: A Review
Masahiko YOSHIMOTO Shintaro IZUMI 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4  pp. 245-259
Type of Manuscript:  INVITED PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
healthcarelow-powerSoCwearable
 Summary | Full Text:PDF(2.3MB)

A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate
Motofumi NAKANISHI Shintaro IZUMI Mio TSUKAHARA Hiroshi KAWAGUCHI Hiromitsu KIMURA Kyoji MARUMOTO Takaaki FUCHIKAMI Yoshikazu FUJIMORI Masahiko YOSHIMOTO 
Publication:   
Publication Date: 2018/04/01
Vol. E101-C  No. 4  pp. 233-242
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
adaptive samplingnormally off computingphysical activity classificationsensor fusionSoC
 Summary | Full Text:PDF(2.4MB)

A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor
Haruki MORI Yohei UMEKI Shusuke YOSHIMOTO Shintaro IZUMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8  pp. 901-908
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
image memorymulti-port SRAM8TFD-SOI28-nmmajority logic
 Summary | Full Text:PDF(1.6MB)

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path
Go MATSUKAWA Yuta KIMI Shuhei YOSHIDA Shintaro IZUMI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/06/01
Vol. E99-A  No. 6  pp. 1198-1205
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
single event effectsingle event upsetsoft error propagationlogical maskingtemporal masking
 Summary | Full Text:PDF(1.7MB)

A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm
Keisuke OKUNO Shintaro IZUMI Kana MASAKI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2592-2599
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
ADPLLfast settlingdigital calibrationtiming error correctiontemperature compensation
 Summary | Full Text:PDF(2.7MB)

Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators
Keisuke OKUNO Toshihiro KONISHI Shintaro IZUMI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1475-1481
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
TDCFSOjitterdesign methodology
 Summary | Full Text:PDF(2.8MB)

An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter
Keisuke OKUNO Toshihiro KONISHI Shintaro IZUMI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/06/01
Vol. E98-C  No. 6  pp. 489-495
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
ADCI/O-sizeVTCMOM capacitance
 Summary | Full Text:PDF(1.8MB)

Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems
Shintaro IZUMI Masanao NAKANO Ken YAMASHITA Yozaburo NAKAI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/05/01
Vol. E98-D  No. 5  pp. 1095-1103
Type of Manuscript:  PAPER
Category: Biological Engineering
Keyword: 
autocorrelationbiomedical signal processingelectrocardiographyheart rate extractionnoise tolerance
 Summary | Full Text:PDF(2.5MB)

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme
Go MATSUKAWA Yohei NAKATA Yasuo SUGURE Shigeru OHO Yuta KIMI Masafumi SHIMOZAWA Shuhei YOSHIDA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4  pp. 333-339
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
dual modular redundancycheckpoint recoveryfault-tolerance
 Summary | Full Text:PDF(3.5MB)

STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier
Yohei UMEKI Koji YANAGIDA Shusuke YOSHIMOTO Shintaro IZUMI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI Koji TSUNODA Toshihiro SUGII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2411-2417
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
STT-MRAMlow-voltageprocess-variation-tolerant
 Summary | Full Text:PDF(3.7MB)

Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell
Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/09/01
Vol. E97-A  No. 9  pp. 1945-1951
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
robust SRAMsoft error rateneutron particlesingle bit upsetmultiple cell upsetnucleus reaction
 Summary | Full Text:PDF(1.9MB)

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation
Yohei NAKATA Yuta KIMI Shunsuke OKUMURA Jinwook JUNG Takuya SAWADA Taku TOSHIKAWA Makoto NAGATA Hirofumi NAKANO Makoto YABUUCHI Hidehiro FUJIWARA Koji NII Hiroyuki KAWAI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4  pp. 332-341
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
design for robustnesscachevariation tolerance7T/14T SRAM
 Summary | Full Text:PDF(4.6MB)

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
Shusuke YOSHIMOTO Shunsuke OKUMURA Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7  pp. 1579-1585
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
SRAMsoft error rate (SER)multiple cell upset (MCU)neutron particletwin welltriple well
 Summary | Full Text:PDF(2.6MB)

A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
Kosuke MIZUNO Kenta TAKAGI Yosuke TERACHI Shintaro IZUMI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 433-443
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
HOGobject detectionlow-powerHDTV
 Summary | Full Text:PDF(5.5MB)

FOREWORD
Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 403-403
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(204.4KB)

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM
Jinwook JUNG Yohei NAKATA Shunsuke OKUMURA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 528-537
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low-voltage adaptive cache designreconfiguring associativitydynamic voltage frequency scaling7T/14T SRAM
 Summary | Full Text:PDF(2.6MB)

A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops
Toshihiro KONISHI Keisuke OKUNO Shintaro IZUMI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 546-552
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
ADCTDCoscillatordigital circuitadaptive LMS filtering
 Summary | Full Text:PDF(2.6MB)

A 168-mW 2.4-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI
Guangji HE Takanobu SUGAHARA Yuki MIYAMOTO Shintaro IZUMI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 444-453
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
40 nm VLSIhidden Markov model (HMM)large vocabulary continuous recognition (LVCSR)
 Summary | Full Text:PDF(3.2MB)

An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter
Toshihiro KONISHI Keisuke OKUNO Shintaro IZUMI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/02/01
Vol. E96-A  No. 2  pp. 434-442
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
ADCTDCoscillatornoise-shapinglow-powersmall areaprocess scalable
 Summary | Full Text:PDF(3.2MB)

A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
Shunsuke OKUMURA Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2226-2233
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
SRAMchip IDphysical unclonable function (PUF)
 Summary | Full Text:PDF(1.9MB)

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
Shusuke YOSHIMOTO Takuro AMASHITA Shunsuke OKUMURA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/10/01
Vol. E95-C  No. 10  pp. 1675-1681
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
SRAMsoft errormultiple-bit upset (MBU)single-event upset (SEU)error correction coding (ECC)alpha particleneutron particle
 Summary | Full Text:PDF(2.6MB)

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
Shusuke YOSHIMOTO Takuro AMASHITA Shunsuke OKUMURA Koji NII Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8  pp. 1359-1365
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
SRAMsingle-event upset (SEU)bit error rate (BER)soft error rate (SER)neutron particlealpha particle
 Summary | Full Text:PDF(4MB)

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
Yohei NAKATA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 523-533
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
network-on-chipprocess variationadaptive circuitsrouting algorithm
 Summary | Full Text:PDF(2.2MB)

A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
Shunsuke OKUMURA Hidehiro FUJIWARA Kosuke YAMAGUCHI Shusuke YOSHIMOTO Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 579-585
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
SRAMFD-SOIInter-die variation
 Summary | Full Text:PDF(1.8MB)

FOREWORD
Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 413-413
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(94.7KB)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
Shusuke YOSHIMOTO Masaharu TERADA Shunsuke OKUMURA Toshikazu SUZUKI Shinji MIYANO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 572-578
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
SRAM8Tlow energydisturbhalf selectwrite back
 Summary | Full Text:PDF(1.9MB)

Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes
Takashi MATSUDA Shintaro IZUMI Yasuharu SAKAI Takashi TAKEUCHI Hidehiro FUJIWARA Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/01/01
Vol. E95-B  No. 1  pp. 178-188
Type of Manuscript:  PAPER
Category: Network
Keyword: 
wireless sensor networkdata aggregationdata storage managementSRAM
 Summary | Full Text:PDF(2MB)

A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
Toshihiro KONISHI Hyeokjong LEE Shintaro IZUMI Takashi TAKEUCHI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2701-2708
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
multi-phase oscillatortransfer gate phase couplereven-numbered phaseslow-powerprocess scalable
 Summary | Full Text:PDF(3MB)

7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
Shunsuke OKUMURA Yuki KAGIYAMA Yohei NAKATA Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2693-2700
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
SRAM DMAtransactional memorycheckpoint and recoverymulti-core processor
 Summary | Full Text:PDF(3.2MB)

A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
Toshihiro KONISHI Shintaro IZUMI Koh TSURUDA Hyeokjong LEE Takashi TAKEUCHI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11  pp. 2287-2294
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Mobile Information Network and Personal Communications
Keyword: 
MRSSmulti-resolution spectrum sensingcognitive radiowireless sensor networklow power
 Summary | Full Text:PDF(1.8MB)

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition
Kosuke MIZUNO Hiroki NOGUCHI Guangji HE Yosuke TERACHI Tetsuya KAMINO Tsuyoshi FUJINAGA Shintaro IZUMI Yasuo ARIKI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 448-457
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
SIFTimage recognitionlow-powerHDTV
 Summary | Full Text:PDF(3.2MB)

VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
Hiroki NOGUCHI Kazuo MIURA Tsuyoshi FUJINAGA Takanobu SUGAHARA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 458-467
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architecture
 Summary | Full Text:PDF(1.8MB)

A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design
Shintaro IZUMI Takashi TAKEUCHI Takashi MATSUDA Hyeokjong LEE Toshihiro KONISHI Koh TSURUDA Yasuharu SAKAI Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 261-269
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
cross-layer designsensor networkssensor nodeMAC protocoltime synchronizationlow power
 Summary | Full Text:PDF(1.6MB)

A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
Takashi TAKEUCHI Shinji MIKAMI Hyeokjong LEE Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 815-821
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
wireless sensor networkamplifier
 Summary | Full Text:PDF(975.5KB)

A Dependable SRAM with 7T/14T Memory Cells
Hidehiro FUJIWARA Shunsuke OKUMURA Yusuke IGUCHI Hiroki NOGUCHI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 423-432
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
SRAMdependabilityquality of a bit
 Summary | Full Text:PDF(1.5MB)

Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
Takashi TAKEUCHI Yu OTAKE Masumi ICHIEN Akihiro GION Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/11/01
Vol. E91-B  No. 11  pp. 3480-3488
Type of Manuscript:  Special Section PAPER (Special Section on Emerging Technologies for Practical Ubiquitous and Sensor Networks)
Category: 
Keyword: 
cross-layer designcrystal oscillatorlong-wave standard time codelow power listeningMAC
 Summary | Full Text:PDF(823.8KB)

Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
Shintaro IZUMI Takashi TAKEUCHI Takashi MATSUDA Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/11/01
Vol. E91-B  No. 11  pp. 3489-3498
Type of Manuscript:  Special Section PAPER (Special Section on Emerging Technologies for Practical Ubiquitous and Sensor Networks)
Category: 
Keyword: 
sensor networkbroadcastfloodingcounter-based scheme
 Summary | Full Text:PDF(1005.5KB)

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
Yuichiro MURACHI Junichi MIYAKOSHI Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Fang YIN Jangchung LEE Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 465-478
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
low powermotion estimationH.264systolic arrayMBAFFSRAM
 Summary | Full Text:PDF(1.8MB)

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
Hiroki NOGUCHI Yusuke IGUCHI Hidehiro FUJIWARA Shunsuke OKUMURA Yasuhiro MORITA Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 543-552
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
8T SRAM cell10T SRAM celllow-power SRAMnon-precharge SRAMtwo-port SRAMvideo processing
 Summary | Full Text:PDF(2.1MB)

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
Yuichiro MURACHI Yuki FUKUYAMA Ryo YAMAMOTO Junichi MIYAKOSHI Hiroshi KAWAGUCHI Hajime ISHIHARA Masayuki MIYAMA Yoshio MATSUDA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 457-464
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
optical flowreal-time video recognitionVLSI processor
 Summary | Full Text:PDF(1.2MB)

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme
Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Yusuke IGUCHI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2695-2702
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Memory Design and Test
Keyword: 
6T SRAM cell8T SRAM cellVth variation
 Summary | Full Text:PDF(1.7MB)

Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks
Takashi MATSUDA Masumi ICHIEN Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/12/01
Vol. E90-B  No. 12  pp. 3410-3418
Type of Manuscript:  Special Section PAPER (Special Section on Ubiquitous Sensor Networks)
Category: 
Keyword: 
sensor networkdata gatheringschedulingcross-layer
 Summary | Full Text:PDF(703.2KB)

Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE 802.11e WLANs
Augusto FORONDA Yuhi HIGUCHI Chikara OHTA Masahiko YOSHIMOTO Yoji OKADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/11/01
Vol. E90-B  No. 11  pp. 3158-3169
Type of Manuscript:  PAPER
Category: Network
Keyword: 
wireless networkbandwidth optimizationbounded delayscheduler
 Summary | Full Text:PDF(1MB)

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes
Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Yusuke IGUCHI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1949-1956
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Next-Generation Memory for SoC
Keyword: 
6T SRAM cell8T SRAM cellVth variation
 Summary | Full Text:PDF(1.8MB)

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond
Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3634-3641
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
SRAMDVSVth-variation-tolerantlow power
 Summary | Full Text:PDF(1.2MB)

A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline
Kentaro KAWAKAMI Jun TAKEMURA Mitsuhiko KURODA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3642-3651
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
H.264/AVCDVS (dynamic voltage scaling)elastic pipelinelow powerdivided entropy decoder
 Summary | Full Text:PDF(1.3MB)

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture
Junichi MIYAKOSHI Yuichiro MURACHI Tetsuro MATSUNO Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3623-3633
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low powermotion estimationH.264SIMDsystolic array
 Summary | Full Text:PDF(1.9MB)

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
Junichi MIYAKOSHI Yuichiro MURACHI Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1629-1636
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
SRAMlow powerparallel processingimage signal processingH.264MPEG
 Summary | Full Text:PDF(1.7MB)

Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks
Shinji MIKAMI Takafumi AONISHI Hironori YOSHINO Chikara OHTA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/10/01
Vol. E89-B  No. 10  pp. 2741-2751
Type of Manuscript:  Special Section PAPER (Special Section on Mobile Multimedia Communications)
Category: 
Keyword: 
sensor networksaggregation efficiencygreedy incremental tree routing
 Summary | Full Text:PDF(989.1KB)

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation
Noriyuki MINEGISHI Junichi MIYAKOSHI Yuki KURODA Tadayoshi KATAGIRI Yuki FUKUYAMA Ryo YAMAMOTO Masayuki MIYAMA Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 230-242
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: System LSIs and Microprocessors
Keyword: 
optical flowprocessor architecturevideo segmentation
 Summary | Full Text:PDF(4.2MB)

Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era
Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Jun TAKEMURA Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3290-3297
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
low powerdynamic voltage frequency scaling (DVFS)adaptive body biasingVdd-hoppingVth-hopping
 Summary | Full Text:PDF(686.3KB)

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application
Yuichiro MURACHI Koji HAMANO Tetsuro MATSUNO Junichi MIYAKOSHI Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3492-3499
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low powermotion estimationMPEG2HDTVIP
 Summary | Full Text:PDF(1.7MB)

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation
Junichi MIYAKOSHI Yuichiro MURACHI Koji HAMANO Tetsuro MATSUNO Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 559-569
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
motion estimationMPEGH.264block-matching
 Summary | Full Text:PDF(719.6KB)

FOREWORD
Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 427-428
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(40.3KB)

A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU
Hideo OHIRA Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 457-465
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
MPEG4 encoderlow powerfeed-forward voltage controlmulti-regulated voltage CPU
 Summary | Full Text:PDF(1.9MB)

A Single Chip H.32X Multimedia Communication Processor with CIF 30 fr/s MPEG-4/H.26X Bi-directional Codec
Noriyuki MINEGISHI Ken-ichi ASANO Keisuke OKADA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 482-490
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
heterogeneous multiple processorsmultimedia communicationH.32xMPEG-4H.26x
 Summary | Full Text:PDF(1.8MB)

VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding
Masayuki MIYAMA Junichi MIYAKOSHI Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 466-474
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
MPEGmotion estimationgradient based methodsteepest descent methodlow powerVLSI
 Summary | Full Text:PDF(731.6KB)

An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video
Masayuki MIYAMA Osamu TOOYAMA Naoki TAKAMATSU Tsuyoshi KODAKE Kazuo NAKAMURA Ai KATO Junichi MIYAKOSHI Kousuke IMAMURA Hideo HASHIMOTO Satoshi KOMATSU Mikio YAGI Masao MORIMOTO Kazuo TAKI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 561-569
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
HDTVMPEGmotion estimation processorGradient Descent Search algorithmSIMD datapath architecture
 Summary | Full Text:PDF(1.1MB)

A Low Power Media Processor Core Performable CIF30 fr/s MPEG4/H26x Video Codec
Hideo OHIRA Toshihisa KAMEMARU Hirokazu SUZUKI Ken-ichi ASANO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 157-165
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLSImedia processor corevideo codinglow powerhigh performance
 Summary | Full Text:PDF(521.6KB)

A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite
Eiji ARITA Takashi FUJIWARA Kin-ichiro NISHIYAMA Akiko MAENO Yasuo MATSUNAMI Masahiko NAKAMURA Hirohisa MACHIDA Shuji MURAKAMI Hiroyuki NAKAYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 166-174
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
BS digitalcarrier recoveryclock recoverydigital demodulation
 Summary | Full Text:PDF(1.2MB)

A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores
Tetsuya MATSUMURA Satoshi KUMAKI Hiroshi SEGAWA Kazuya ISHIHARA Atsuo HANAMI Yoshinori MATSUURA Stefan SCOTZNIOVSKY Hidehiro TAKATA Akira YAMADA Shu MURAYAMA Tetsuro WADA Hideo OHIRA Toshiaki SHIMADA Ken-ichi ASANO Toyohiko YOSHIDA Masahiko YOSHIMOTO Koji TSUCHIHASHI Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/01/01
Vol. E84-C  No. 1  pp. 108-122
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
video encoderMPEG-2media-processoraudio encodersystem encodermotion estimation
 Summary | Full Text:PDF(2.1MB)

An Architectural Study of an MPEG-2 422P@HL Encoder Chip Set
Ayako HARADA Shin-ichi HATTORI Tadashi KASEZAWA Hidenori SATO Tetsuya MATSUMURA Satoshi KUMAKI Kazuya ISHIHARA Hiroshi SEGAWA Atsuo HANAMI Yoshinori MATSUURA Ken-ichi ASANO Toyohiko YOSHIDA Masahiko YOSHIMOTO Tokumichi MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8  pp. 1614-1623
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Implementations of Signal Processing Systems
Keyword: 
video compressionvideo encoderMPEG-2HDTVmotion estimation
 Summary | Full Text:PDF(2.9MB)

A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder
Tetsuya MATSUMURA Hiroshi SEGAWA Satoshi KUMAKI Yoshinori MATSUURA Atsuo HANAMI Kazuya ISHIHARA Shin-ichi NAKAGAWA Tadashi KASEZAWA Yoshihide AJIOKA Atsushi MAEDA Masahiko YOSHIMOTO Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 680-694
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
video compression/decompressionvideo encoderMPEG2video signal processor
 Summary | Full Text:PDF(1.9MB)

ULSI Realization of MPEG2 Realtime Video Encoder and Decoder--An Overview
Masahiko YOSHIMOTO Shin-ichi NAKAGAWA Tetsuya MATSUMURA Kazuya ISHIHARA Shin-ichi URAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12  pp. 1668-1681
Type of Manuscript:  INVITED PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
video compression/decompressionvideo encodervideo decoderMPEG2video signal processor
 Summary | Full Text:PDF(1.1MB)

An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
Shin-ichi URAMOTO Akihiko TAKABATAKE Takashi HASHIMOTO Jun TAKEDA Gen-ichi TANAKA Tsuyoshi YAMADA Yukio KODAMA Atsushi MAEDA Toshiaki SHIMADA Shun-ichi SEKIGUCHI Tokumichi MURAKAMI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12  pp. 1697-1708
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
image compressionvideo decoderMPEG2
 Summary | Full Text:PDF(1.1MB)

A Highly Parallel DSP Architecture for Image Recognition
Hiroyuki KAWAI Yoshitsugu INOUE Rebert STREITENBERGER Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/08/25
Vol. E78-A  No. 8  pp. 963-970
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
image recognitionSIMDDSParchitecture
 Summary | Full Text:PDF(727.1KB)

A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video
Shin-ichi URAMOTO Akihiko TAKABATAKE Mitsuyoshi SUZUKI Hiroki SAKURAI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12  pp. 1930-1936
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processors
Keyword: 
image compressionmotion estimationsystolic array
 Summary | Full Text:PDF(718.3KB)

A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
Jun TAKEDA Shin-ichi URAMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/01/25
Vol. E77-A  No. 1  pp. 272-280
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
error analysismean-squared errordistributed arithmeticDCT/IDCT
 Summary | Full Text:PDF(660.5KB)

Future Technological and Economic Prospects for VLSI
Hiroyoshi KOMIYA Masahiko YOSHIMOTO Hidenobu ISHIKURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1555-1563
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
VLSI technology and economics
 Summary | Full Text:PDF(782.1KB)

A 100-MHz 2-D Discrete Cosine Transform Core Processor
Shin-ichi URAMOTO Yoshitsugu INOUE Akihiko TAKABATAKE Jun TAKEDA Yukihiro YAMASHITA Hideyuki TERANE Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 390-397
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF(759KB)

A High-Performance Reconfigurable Line Memory Macrocell for Video Signal Processing ASICs
Tetsuya MATSUMURA Masahiko YOSHIMOTO Atsushi MAEDA Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C  No. 11  pp. 3787-3795
Type of Manuscript:  Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Core and Macrocells
Keyword: 
 Summary | Full Text:PDF(986.5KB)