IEICE Trans

Masahide TAKADA

Hierarchical Word-Line Architecture for Large Capacity DRAMs Tatsunori MUROTANI Tadahiko SUGIBAYASHI Masahide TAKADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-C No. 4 pp. 550-556 Type of Manuscript: INVITED PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Memory LSI Keyword: DRAM, hierarchical word line, partial subarray activation,
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PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs Kazuyuki NAKAMURA Shigeru KUHARA Thoru KIMURA Masahide TAKADA Hisamitsu SUZUKI Hiroshi YOSHIDA Tohru YAMAZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 pp. 805-811 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword:
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FOREWORD Masahide TAKADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 pp. 765-765 Type of Manuscript: FOREWORD Category: Keyword:
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BIST Circuit Macro Using Microprogram ROM for LSI Memories Hiroki KOIKE Toshio TAKESHIMA Masahide TAKADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 pp. 838-844 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: memory, BIST, ROM, tester, macro,
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Reviews and Prospects of SRAM Technology Masahide TAKADA Tadayoshi ENOMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/25 Vol. E74-C No. 4 pp. 827-838 Type of Manuscript: INVITED PAPER (Special Issue on LSI Memories) Category: SRAM Keyword:
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Logic Functional Level Converter for High Speed Address Decoder of ECL I/O BiCMOS SRAMs Kazuyuki NAKAMURA Masahide TAKADA Toshio TAKESHIMA Kouichirou FURUTA Tohru YAMAZAKI Kiyotaka IMAI Susumu OHI Yumi SEKINE Yukio MINATO Hisamitsu KIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/25 Vol. E74-C No. 4 pp. 845-852 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: SRAM Keyword:
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A 65 Kbit Dynamic RAM Using Short Channel MOS FETs Masahide TAKADA Toshio TAKESHIMA Shunichi SUZUKI Mitsuru SAKAMOTO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1979/07/25 Vol. E62-E No. 7 pp. 484-485 Type of Manuscript: LETTER Category: Integrated Circuits Keyword:
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