IEICE Trans

Manabu KOBAYASHI

Probabilistic Fault Diagnosis and its Analysis in Multicomputer Systems Manabu KOBAYASHI Toshiyasu MATSUSHIMA Shigeichi HIRASAWA
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2072-2081 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding theory and techniques Keyword: multicomputer systems, system-level fault diagnosis, probabilistic fault diagnosis, intermittent faults, density evolution,
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Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs Manabu KOBAYASHI Hiroshi NINOMIYA Yasuyuki MIURA Shigeyoshi WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/05/01 Vol. E97-A No. 5 pp. 1051-1058 Type of Manuscript: PAPER Category: Circuit Theory Keyword: reconfigurable logic circuit, ambipolar double-gate devices, dynamic logic, CNTFETs,
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Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs Hiroshi NINOMIYA Manabu KOBAYASHI Yasuyuki MIURA Shigeyoshi WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/02/01 Vol. E97-A No. 2 pp. 675-678 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: reconfigurable logic circuit design, ambipolar device, double-gate CNTFET, binary decision diagram, arithmetic logic unit,
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Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs Manabu KOBAYASHI Hiroshi NINOMIYA Shigeyoshi WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/07/01 Vol. E96-A No. 7 pp. 1642-1644 Type of Manuscript: LETTER Category: Circuit Theory Keyword: reconfigurable logic circuit, ambipolar double-gate devices, dynamic logic, CNTFETs,
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Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram Hiroshi NINOMIYA Manabu KOBAYASHI Shigeyoshi WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/01/01 Vol. E96-A No. 1 pp. 356-359 Type of Manuscript: LETTER Category: Circuit Theory Keyword: reconfigurable logic design, ambipolar device, double gate CNTFET, binary decision diagram,
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Adaptive Decoding Algorithms for Low-Density Parity-Check Codes over the Binary Erasure Channel Gou HOSOYA Hideki YAGI Manabu KOBAYASHI Shigeichi HIRASAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/10/01 Vol. E92-A No. 10 pp. 2418-2430 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: low-density parity-check code, belief-propagation decoding, binary erasure channel, stopping set,
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Density Evolution Analysis of Robustness for LDPC Codes over the Gilbert-Elliott Channel Manabu KOBAYASHI Hideki YAGI Toshiyasu MATSUSHIMA Shigeichi HIRASAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/10/01 Vol. E91-A No. 10 pp. 2754-2764 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: LDPC codes, density evolution, Gilbert-Elliott channel, robustness,
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An Improved Method of Reliability-Based Maximum Likelihood Decoding Algorithms Using an Order Relation among Binary Vectors Hideki YAGI Manabu KOBAYASHI Toshiyasu MATSUSHIMA Shigeichi HIRASAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/10/01 Vol. E87-A No. 10 pp. 2493-2502 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: maximum likelihood decoding, soft decision decoding, reliability measure, linear block codes, order relation,
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Complexity Reduction of the Gazelle and Snyders Decoding Algorithm for Maximum Likelihood Decoding Hideki YAGI Manabu KOBAYASHI Shigeichi HIRASAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/10/01 Vol. E86-A No. 10 pp. 2461-2472 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: maximum likelihood decoding, information set decoding, most reliable basis, reliability measure, linear block codes,
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An Efficient Heuristic Search Method for Maximum Likelihood Decoding of Linear Block Codes Using Dual Codes Tomotsugu OKADA Manabu KOBAYASHI Shigeichi HIRASAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/02/01 Vol. E85-A No. 2 pp. 485-489 Type of Manuscript: PAPER Category: Coding Theory Keyword: block codes, soft decision, maximum likelihood decoding, A^* algorithm, dual codes,
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