Manabu ARAKAKI


Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing
Takahiro HANYU Manabu ARAKAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 948-955
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multiple-Valued Architectures
Keyword: 
logic value conversion (LVC)floating-gate MOS transistorthreshold operationsingle-transistor cellfully parallel template matching
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