Mamoru FUJITA


A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs
Tadahiko SUGIBAYASHI Isao NARITAKE Hiroshi TAKADA Ken INOUE Ichiro YAMAMOTO Tatsuya MATANO Mamoru FUJITA Yoshiharu AIMOTO Toshio TAKESHIMA Satoshi UTSUGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1323-1327
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
memoryDRAMtest
 Summary | Full Text:PDF(588.5KB)

Design Rule Relaxation Approach for High-Density DRAMs
Takanori SAEKI Eiichiro KAKEHASHI Hidemitu MORI Hiroki KOGA Kenji NODA Mamoru FUJITA Hiroshi SUGAWARA Kyoichi NAGATA Shozo NISHIMOTO Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3  pp. 406-415
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
DRAMdesign ruleclose packed cell arrayBoosted Dual Word-Line scheme
 Summary | Full Text:PDF(1.1MB)