IEICE Trans

Makoto SUGIHARA

Minimization of the Fabrication Cost for a Bridged-Bus-Based TDMA System under Hard Real-Time Constraints Makoto SUGIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/12/01 Vol. E97-D No. 12 pp. 3041-3051 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Network Keyword: bridged buses, fabrication cost, scheduling, time division multiple access, FlexRay,
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A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors Makoto SUGIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 477-486 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: soft error, NBTI, SEU, SET, control signal error, continuous signature monitoring, reliability, vulnerability, microprocessor,
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On Synthesizing a Reliable Multiprocessor for Embedded Systems Makoto SUGIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2560-2569 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: heterogeneous multiprocessor synthesis, soft error, single event upset, reliability, real-time system,
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Character-Size Optimization for Reducing the Number of EB Shots of MCC Lithographic Systems Makoto SUGIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/05/01 Vol. E93-C No. 5 pp. 631-639 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Manufacturing Technology Keyword: maskless lithography, character projection, variable-shaped beam, multi-column-cell system, character size optimization, EB shots,
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Reliability Inherent in Heterogeneous Multiprocessor Systems and Task Scheduling for Ameliorating Their Reliability Makoto SUGIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1121-1128 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: soft error, single event upset, reliability, task scheduling, heterogeneous multiprocessor systems,
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Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems Makoto SUGIHARA Yusuke MATSUNAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3451-3460 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: maskless lithography, multi-column-cells, character projection, variable-shaped beam, throughput,
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Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 410-417 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: single event upset, SRAM, DRAM, reliability, cache architecture, task scheduling,
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Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1983-1991 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: VLSI Design Technology Keyword: soft error, reliability, estimation, computer systems, instruction-set simulation,
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Technology Mapping Technique for Increasing Throughput of Character Projection Lithography Makoto SUGIHARA Kenta NAKAMURA Yusuke MATSUNAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/05/01 Vol. E90-C No. 5 pp. 1012-1020 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Lithography-Related Techniques Keyword: maskless lithography, character projection, variable-shaped beam, technology mapping, throughput,
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Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment Makoto SUGIHARA Taiga TAKATA Kenta NAKAMURA Ryoichi INANAMI Hiroaki HAYASHI Katsumi KISHIMOTO Tetsuya HASEBE Yukihiro KAWANO Yusuke MATSUNAGA Kazuaki MURAKAMI Katsuya OKUMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 377-383 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: CAD Keyword: cell library, character projection, electron beam, EB shots, throughput, optimization, integer linear programming,
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Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints Makoto SUGIHARA Kazuaki MURAKAMI Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3174-3184 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: core-based design, SOC, TAM, test architecture, floorplan, test scheduling,
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Optimization of Test Accesses with a Combined BIST and External Test Scheme Makoto SUGIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2731-2738 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: test time, BIST, external test, CBET, test scheduling, test access, test bus, external pins,
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Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores Vikram IYENGAR Hiroshi DATE Makoto SUGIHARA Krishnendu CHAKRABARTY
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2632-2638 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: IP Protection Keyword: core partitioning, embedded core testing, intellectual property, partially-mergeable cores, test access mechanism (TAM),
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A Test Methodology for Core-Based System LSIs Makoto SUGIHARA Hiroshi DATE Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2640-2645 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: testing time, core-based system LSI, BIST, external testing,
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