IEICE Trans

Makoto NAGATA

FOREWORD Makoto NAGATA
Publication: Publication Date: 2021/07/01 Vol. E104-C No. 7 pp. 261-261 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

Secure Cryptographic Unit as Root-of-Trust for IoT Era Tsutomu MATSUMOTO Makoto IKEDA Makoto NAGATA Yasuyoshi UEMURA
Publication: Publication Date: 2021/07/01 Vol. E104-C No. 7 pp. 262-271 Type of Manuscript: INVITED PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: IoT, security IP, public-key cryptography, root of trust,
	Summary \| Full Text:PDF

A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation Yoshihide KOMATSU Akinori SHINMYO Mayuko FUJITA Tsuyoshi HIRAKI Kouichi FUKUDA Noriyuki MIURA Makoto NAGATA
Publication: Publication Date: 2020/10/01 Vol. E103-C No. 10 pp. 497-504 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Electronic Circuits Keyword: adaptive voltage, transmitter, forward-body-bias (FBB), self-adjusted, threshold voltage, aggressor, jitter estimation, process-voltage-temperature (PVT), clock data recovery (CDR),
	Summary \| Full Text:PDF

FOREWORD Makoto NAGATA
Publication: Publication Date: 2020/04/01 Vol. E103-C No. 4 pp. 131-131 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

A 0.72pJ/bit 400μm² Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes Takuji MIKI Noriyuki MIURA Makoto NAGATA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 530-537 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: hardware security, physical random number, random masking, SAR ADC,
	Summary \| Full Text:PDF

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS Takuji MIKI Noriyuki MIURA Kento MIZUTA Shiro DOSHO Makoto NAGATA
Publication: Publication Date: 2017/06/01 Vol. E100-C No. 6 pp. 560-567 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: Voltage-to-Time converter (VTC), time domain processing, CMOS, two-step transition, trip voltage,
	Summary \| Full Text:PDF

Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator Naoya AZUMA Shunsuke SHIMAZAKI Noriyuki MIURA Makoto NAGATA Tomomitsu KITAMURA Satoru TAKAHASHI Motoki MURAKAMI Kazuaki HORI Atsushi NAKAMURA Kenta TSUKAMOTO Mizuki IWANAMI Eiji HANKUI Sho MUROGA Yasushi ENDO Satoshi TANAKA Masahiro YAMAGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/06/01 Vol. E97-C No. 6 pp. 546-556 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: substrate coupling, power delivery network, noise interference, wireless communication,
	Summary \| Full Text:PDF

Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking Satoshi TAKAYA Hiroaki IKEDA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/06/01 Vol. E97-C No. 6 pp. 557-565 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: wide I/O bus, through silicon via, signal integrity, power integrity,
	Summary \| Full Text:PDF

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation Yohei NAKATA Yuta KIMI Shunsuke OKUMURA Jinwook JUNG Takuya SAWADA Taku TOSHIKAWA Makoto NAGATA Hirofumi NAKANO Makoto YABUUCHI Hidehiro FUJIWARA Koji NII Hiroyuki KAWAI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 332-341 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: design for robustness, cache, variation tolerance, 7T/14T SRAM,
	Summary \| Full Text:PDF

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage Daisuke FUJIMOTO Noriyuki MIURA Makoto NAGATA Yuichi HAYASHI Naofumi HOMMA Takafumi AOKI Yohei HORI Toshihiro KATASHITA Kazuo SAKIYAMA Thanh-Ha LE Julien BRINGER Pirouz BAZARGAN-SABET Shivam BHASIN Jean-Luc DANGER
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 272-279 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: information leakage, side-channel attack, correlation power analysis, advance encryption standard,
	Summary \| Full Text:PDF

AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model Kumpei YOSHIKAWA Kouji ICHIKAWA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 264-271 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: power supply noise, electromagnetic compatibility, LSI chip-package-board co-design, power integrity,
	Summary \| Full Text:PDF

Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring Yuuki ARAGA Nao UEDA Yasumasa TAKAGI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2516-2523 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: behavioral modeling, waveform data acquisition, power supply noise, substrate noise, diagnosis of VLSI circuits,
	Summary \| Full Text:PDF

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation Daisuke FUJIMOTO Toshihiro KATASHITA Akihiko SASAKI Yohei HORI Akashi SATOH Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2533-2541 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: power supply current, electromagnetic leakage, information leakage, AES,
	Summary \| Full Text:PDF

Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components Naoya AZUMA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 pp. 875-883 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: mixed signal VLSI circuit, substrate crosstalk, power integrity, substrate network model,
	Summary \| Full Text:PDF

Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation Satoshi TAKAYA Yoji BANDO Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Masaaki SOUDA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 pp. 884-893 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: mixed signal VLSI circuit, substrate crosstalk, on-chip noise monitoring,
	Summary \| Full Text:PDF

Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits Takeshi OKUMOTO Kumpei YOSHIKAWA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 538-545 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: noise detection circuit, power supply noise, power supply integrity, systems-on-a-chip,
	Summary \| Full Text:PDF

Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits Kumpei YOSHIKAWA Yuta SASAKI Kouji ICHIKAWA Yoshiyuki SAITO Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2284-2291 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: LSI chip-package-board co-design, electromagnetic compatibility, power supply noise, power delivery network,
	Summary \| Full Text:PDF

FOREWORD Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/06/01 Vol. E95-C No. 6 pp. 977-977 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation Takuya SAWADA Taku TOSHIKAWA Kumpei YOSHIKAWA Hidehiro TAKATA Koji NII Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 586-593 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: SRAM, Immunity, On chip monitoring, Built-in self testing,
	Summary \| Full Text:PDF

Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/02/01 Vol. E95-A No. 2 pp. 430-438 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: substrate noise, substrate crosstalk, substrate integrity, power supply integrity, mixed analog digital circuits, very large scale integration,
	Summary \| Full Text:PDF

On-Chip In-Place Measurements of V_th and Signal/Substrate Response of Differential Pair Transistors Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Masaaki SOUDA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/01/01 Vol. E95-C No. 1 pp. 137-145 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: on-chip monitor, substrate noise, differential amplifier,
	Summary \| Full Text:PDF

A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength Takushi HASHIDA Yuuki ARAGA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1016-1023 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: on-chip diagnosis, on-chip monitoring,
	Summary \| Full Text:PDF

On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement Masaaki SODA Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1024-1031 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: noise, sine wave, harmonic,
	Summary \| Full Text:PDF

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Masaaki SOUDA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 495-503 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: on-chip monitor, power supply noise,
	Summary \| Full Text:PDF

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology Tetsuro MATSUNO Daisuke FUJIMOTO Daisuke KOSAKA Naoyuki HAMANISHI Ken TANABE Masazumi SHIOCHI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 pp. 820-826 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: noise emulation, substrate noise, power supply noise, signal integrity, substrate coupling, power integrity,
	Summary \| Full Text:PDF

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails Takushi HASHIDA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 pp. 842-848 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: power-line communication, on-chip diagnosis, signal integrity, power integrity, mixed-signal circuit,
	Summary \| Full Text:PDF

Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits Tetsuro MATSUNO Daisuke KOSAKA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/02/01 Vol. E93-A No. 2 pp. 440-447 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: substrate noise, power supply noise, signal integrity, substrate coupling, power integrity,
	Summary \| Full Text:PDF

Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations Mitsuya FUKAZAWA Masanori KURIMOTO Rei AKIYAMA Hidehiro TAKATA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 pp. 475-482 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: power supply voltage noise built-in probing circuit, failure susceptibility, dynamic frequency scaling,
	Summary \| Full Text:PDF

Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications Takefumi YOSHIKAWA Tetsuhiro OGINO Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 pp. 1453-1462 Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation) Category: Keyword: interface, current mode, low power, low EMI noise,
	Summary \| Full Text:PDF

Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation Kouji ICHIKAWA Yuki TAKAHASHI Yukihiko SAKURAI Takahiro TSUDA Isao IWASE Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/06/01 Vol. E91-C No. 6 pp. 936-944 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: integrated circuit, electro magnetic interference, on-chip monitor, immunity,
	Summary \| Full Text:PDF

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification Daisuke KOSAKA Makoto NAGATA Yoshitaka MURASAKA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2651-2660 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: chip-level substrate coupling, F-matrix computation, slice-and-stack substrate modeling,
	Summary \| Full Text:PDF

A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System Yohei FUKUMIZU Naoki GOCHI Makoto NAGATA Kazuo TAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1299-1303 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: RFID, anti-collision, TH-CDMA, integrated multi-level simulation environment, behavioral modeling, Verilog-AMS,
	Summary \| Full Text:PDF

Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements Kouji ICHIKAWA Yuki TAKAHASHI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1282-1290 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: large scale integration, electro magnetic interference, printed circuit board, signal integrity, power supply integrity, integrated analysis,
	Summary \| Full Text:PDF

On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration Koichiro NOGUCHI Takushi HASHIDA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1189-1196 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: SoC, analog diagnosis, on-chip monitor,
	Summary \| Full Text:PDF

Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations Masao MORIMOTO Makoto NAGATA Kazuo TAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 675-682 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: ASDMDL, differential logic, high-speed logic, low-power logic,
	Summary \| Full Text:PDF

Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias Yoshihide KOMATSU Koichiro ISHIBASHI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 692-698 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: substrate noise, random variability, forward body bias, self adjusted, impurities, latch-up, CMOS, SoC,
	Summary \| Full Text:PDF

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits Daisuke KOSAKA Makoto NAGATA Yoshitaka MURASAKA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/02/01 Vol. E90-A No. 2 pp. 380-387 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: substrate coupling, equivalent circuit modeling, guard ring, guard band, deep n-well, substrate noise analysis, S21 measurement, F-matrix computation,
	Summary \| Full Text:PDF

Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise Mitsuya FUKAZAWA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1559-1566 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: delay variation, dynamic power supply noise, static IR drop, on-chip waveform monitor circuit, signal integrity,
	Summary \| Full Text:PDF

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs Kenji SHIMAZAKI Makoto NAGATA Mitsuya FUKAZAWA Shingo MIYAHARA Masaaki HIRATA Kazuhiro SATOH Hiroyuki TSUJIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1535-1543 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: power-supply noise, ground noise, noise detector, dynamic IR drop, timing analysis,
	Summary \| Full Text:PDF

Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach Yohei FUKUMIZU Makoto NAGATA Kazuo TAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1581-1590 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: RFID, anti-collision, TH-CDMA, high-level modeling, back-end design, top-down approach, robustness,
	Summary \| Full Text:PDF

An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity Koichiro NOGUCHI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 pp. 761-768 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: signal integrity, substrate crosstalk, delay variation, on-chip monitor,
	Summary \| Full Text:PDF

Multi-Ported Register File for Reducing the Impact of PVT Variation Yuuichirou IKEDA Masaya SUMITA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 356-363 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Signal Integrity and Variability Keyword: multi-ported register file, self timing circuits, PVT variation, crosstalk noise,
	Summary \| Full Text:PDF

Communication Scheme for a Highly Collision-Resistive RFID System Yohei FUKUMIZU Shuji OHNO Makoto NAGATA Kazuo TAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/02/01 Vol. E89-A No. 2 pp. 408-415 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: RFID, anti-collision, TD-CDMA, low-power, impulse modulation, inductive coupling, hardware emulation,
	Summary \| Full Text:PDF

Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition Masao MORIMOTO Yoshinori TANAKA Makoto NAGATA Kazuo TAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3324-3331 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic synthesis, ASDDL, asymmetric slope, differential logic, high speed,
	Summary \| Full Text:PDF

High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition Masao MORIMOTO Makoto NAGATA Kazuo TAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/10/01 Vol. E88-C No. 10 pp. 2001-2008 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: ASDDL, ASD-CMOS, asymmetric slope, differential logic, high speed,
	Summary \| Full Text:PDF

Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits Kenji SHIMAZAKI Makoto NAGATA Takeshi OKUMOTO Shozo HIRANO Hiroyuki TSUJIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 589-596 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Digital Keyword: substrate noise, power-supply noise, ground noise, noise detector, dynamic IR drop,
	Summary \| Full Text:PDF

Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps Takashi MORIE Kenichi MURAKOSHI Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1856-1862 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: CMOS analog integrated circuits, nonlinear circuits, nonlinear functions, pulse width modulation, pulse phase modulation, chaos,
	Summary \| Full Text:PDF

An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing Kousuke KATAYAMA Atsushi IWATA Takashi MORIE Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/08/01 Vol. E85-C No. 8 pp. 1596-1603 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits) Category: Keyword: Hadamard transform, image sensor, pulse width modulation technique, charge sharing,
	Summary \| Full Text:PDF

Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques Hiroshi ANDO Takashi MORIE Makoto MIYAKE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/02/01 Vol. E85-A No. 2 pp. 381-388 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: resistive-fuse network, oscillator network, image segmentation, image extraction, pulse modulation circuit,
	Summary \| Full Text:PDF

A CMOS Stochastic Associative Processor Using PWM Chaotic Signals Toshio YAMANAKA Takashi MORIE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/12/01 Vol. E84-C No. 12 pp. 1723-1729 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Systems with New Concepts) Category: Keyword: pulse-width modulation, PWM, chaotic signals, stochastic association,
	Summary \| Full Text:PDF

Merged Analog-Digital Circuits Using Pulse Modulation for Intelligent SoC Applications Atsushi IWATA Takashi MORIE Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/02/01 Vol. E84-A No. 2 pp. 486-496 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques Supporting the System LSI Era) Category: Keyword: pulse modulation, mixed analog-digital integrated circuits, nonlinear dynamical systems, switched current integration, time-domain signal processing,
	Summary \| Full Text:PDF

A Nonlinear Oscillator Network for Gray-Level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation Hiroshi ANDO Takashi MORIE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/02/25 Vol. E83-A No. 2 pp. 329-336 Type of Manuscript: Special Section PAPER (Special Section on Intelligent Signal and Image Processing) Category: Keyword: nonlinear oscillator network, LEGION, image segmentation, pulse modulation, PWM, PPM, LSI implementation,
	Summary \| Full Text:PDF

New Non-Volatile Analog Memory Circuits Using PWM Methods Shigeo KINOSHITA Takashi MORIE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1655-1661 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Non-Binary Architectures Keyword: analog memory, floating gate device, pulse width modulation, PWM,
	Summary \| Full Text:PDF

An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique Takashi MORIE Jun FUNAKOSHI Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 356-363 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: LSI implementation, neural network, pulse width modulation, PWM,
	Summary \| Full Text:PDF

Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 271-278 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog-digital mixed LSI, substrate noise, crosstalk, AnalogHDL, behavioral modeling, macroscopic substrate noise model, ΔΣADC,
	Summary \| Full Text:PDF

A Stochastic Associative Memory Using Single-Electron Tunneling Devices Makoto SAEN Takashi MORIE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/01/25 Vol. E81-C No. 1 pp. 30-35 Type of Manuscript: Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices) Category: Keyword: associative memory, single-electron tunneling, SET, single-electron transistor,
	Summary \| Full Text:PDF

A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's Atsushi IWATA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/02/25 Vol. E79-A No. 2 pp. 145-157 Type of Manuscript: Special Section PAPER (Special Section on Analog Technologies in Submicron Era) Category: Keyword: pulse width modulation (PWM), switched current integrator, PWM adder, PWM signal converter,
	Summary \| Full Text:PDF