Liang-Bi CHEN


A Comprehensive Medicine Management System with Multiple Sources in a Nursing Home in Taiwan
Liang-Bi CHEN Wan-Jung CHANG Kuen-Min LEE Chi-Wei HUANG Katherine Shu-Min LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/06/01
Vol. E99-D  No. 6  pp. 1447-1454
Type of Manuscript:  Special Section PAPER (Special Section on Human Cognition and Behavioral Science and Technology)
Category: 
Keyword: 
inappropriate drug useinteractive consultingmedicine managementproactive feedbackreal-time tracking
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An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip
Katherine Shu-Min LI Yingchieh HO Yu-Wei YANG Liang-Bi CHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2320-2329
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Circuit Implementations
Keyword: 
DVFSmeasurement and simulation of multiple-processor (multicores, PSoC) systemsreal-time distributed systemsreliabilitythermal effect control scheme
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Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning
Katherine Shu-Min LI Yingchieh HO Liang-Bi CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2467-2474
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
crosstalkdelay effectsinsertion bufferinterconnect-driven floorplanningnoise-aware buffer planning
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Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip
Katherine Shu-Min LI Chih-Yun PAI Liang-Bi CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2649-2658
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
interconnect fault toleranceinterconnect testinginterconnect diagnosisinterconnect resilienceoscillation ring scheme
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HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms
Liang-Bi CHEN Jiun-Cheng JU Chien-Chou WANG Ing-Jer HUANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2100-2108
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
AMBAdebuggingsystem-on-a-chip (SoC)protocol checkerverification
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A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement
Liang-Bi CHEN Chi-Tsai YEH Hung-Yu CHEN Ing-Jer HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3193-3202
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
design space explorationsystem-on-a-chip (SoC)SystemCUML3D graphics
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