Kyoji YAMASHITA

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential
Dondee NAVARRO Takeshi MIZOGUCHI Masami SUETAKE Kazuya HISAMITSU Hiroaki UENO Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 1079-1086
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
pinch-off region, channel-length modulation, overlap capacitance, surface-potential-based modeling, circuit simulation, 
 Summary | Full Text:PDF
A Test Structure for Two-Dimensional Analysis of MOSFETs by Hot-Carrier-Induced Photoemission
Toshihiro MATSUDA Hiroaki TAKEUCHI Akira MURAMATSU Hideyuki IWATA Takashi OHZONE Kyoji YAMASHITA Norio KOIKE Ken-ichiro TATSUUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 811-816
Type of Manuscript:  Special Section PAPER (Special Section on Microelectronic Test Structures)
Category: 
Keyword: 
MOSFET, photoemission, hot carrier, gate length, 
 Summary | Full Text:PDF
1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation
Shizunori MATSUMOTO Hiroaki UENO Satoshi HOSOKAWA Toshihiko KITAMURA Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Tatsuya OHGURO Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/02/01
Vol. E88-C  No. 2  pp. 247-254
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
100 nm-MOSFET, 1/f noise, measurement, modeling, 
 Summary | Full Text:PDF
Circuit-Simulation Model of Cgd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients
Dondee NAVARRO Hiroaki KAWANO Kazuya HISAMITSU Takatoshi YAMAOKA Masayasu TANAKA Hiroaki UENO Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3  pp. 474-480
Type of Manuscript:  INVITED PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
gate-drain capacitance, surface-potential based modeling, lateral field gradient, pocket-implant technology, 
 Summary | Full Text:PDF
Circuit Simulation Models for Coming MOSFET Generations
Mitiko MIURA-MATTAUSCH Hiroaki UENO Hans Juergen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4  pp. 740-748
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
MOSFET model, surface potential, charge based modeling, sub-100 nm technology, 
 Summary | Full Text:PDF
A Design Hierarchy of IC Interconnects and Gate Patterns
Shinji ODANAKA Akio MISAKA Kyoji YAMASHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6  pp. 948-954
Type of Manuscript:  INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
TCAD, interconnect, OPC, gate pattern, design rule, 
 Summary | Full Text:PDF