Kwang-Hyun BAEK

High-Speed and Low-Complexity Decoding Architecture for Double Binary Turbo Code
Kon-Woo KWON Kwang-Hyun BAEK Jeong Woo LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11  pp. 2458-2461
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
maximum a posteriori probability (MAP) algorithm, double binary turbo decoder, very large scale integration (VLSI), mobile WiMAX, 
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A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform
Jeonghun KIM Suki KIM Kwang-Hyun BAEK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/09/01
Vol. E93-D  No. 9  pp. 2500-2508
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
Bluetooth V2.0, enhanced data rate (EDR), low-power architecture, wireless SOC, sub band codec, platform-based design, verification, 
 Summary | Full Text:PDF
6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator
Yun-Jeong KIM Jong-Ho LEE Ja-Hyun KOO Kwang-Hyun BAEK Suki KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/03/01
Vol. E91-C  No. 3  pp. 392-395
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
comparator, flash ADC, high-speed ADC, interpolation, 
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Digitally Controlled Duty Cycle Corrector with 1 ps Resolution
Youngkwon JO Hoyoung PARK Sanghyuk YANG Suki KIM Kwang-Hyun BAEK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/09/01
Vol. E90-C  No. 9  pp. 1841-1843
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
duty cycle corrector, variable delay unit, delay locked loop, 
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High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers
Edward MERLO Kwang-Hyun BAEK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/05/01
Vol. E88-A  No. 5  pp. 1373-1378
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
phase accumulator, DDFS, NCO, 
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Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems
Kwang-Hyun BAEK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 1053-1060
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
high-speed D/A converter, design methodology, interconnect modeling, behavioral modeling, mixed-mode VLSI, 
 Summary | Full Text:PDF