Kuo-Hsing CHENG


Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture
Yo-Hao TU Jen-Chieh LIU Kuo-Hsing CHENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 655-658
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
static-phase-errordelay-locked-loopfrequency multiplieredge-combinertime amplifier
 Summary | Full Text:PDF

A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit
Shyh-Shyuan SHEU Kuo-Hsing CHENG Yu-Sheng CHEN Pang-Shiu CHEN Ming-Jinn TSAI Yu-Lung LO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/06/01
Vol. E95-C  No. 6  pp. 1128-1131
Type of Manuscript:  BRIEF PAPER
Category: Integrated Electronics
Keyword: 
Resistive RAM (RRAM)verifywrite resistance tracking circuit
 Summary | Full Text:PDF

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application
Kuo-Hsing CHENG Yu-Chang TSAI Chien-Nan Jimmy LIU Kai-Wei HONG Chin-Cheng KUO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/07/01
Vol. E92-C  No. 7  pp. 964-972
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
phase-locked loop (PLL)self-calibrationlow jittermulti-phase VCO
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High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
Yu-Lung LO Wei-Bin YANG Ting-Sheng CHAO Kuo-Hsing CHENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 890-893
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
dynamic D flip-flopscountersprescalersultra-low-voltage design
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Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System
Shu-Yu JIANG Chan-Wei HUANG Yu-Lung LO Kuo-Hsing CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A  No. 2  pp. 389-400
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
built-in jitter measurementVernier caliperequivalent-signal samplingauto focus
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Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing
Kuo-Hsing CHENG Chia-Wei SU Hsin-Hsin KO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/12/01
Vol. E91-C  No. 12  pp. 1941-1950
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
buck convertercurrent-mode controlPWMcurrent-sensinghigh efficiencyhigh accurate
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64-Bit High-Performance Power-Aware Conditional Carry Adder Design
Kuo-Hsing CHENG Shun-Wen CHENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6  pp. 1322-1331
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
conditional sum adderconditional carry adderpower-awarehybrid dual-threshold voltageCMOS design
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A Fast-Lock DLL with Power-On Reset Circuit
Kuo-Hsing CHENG Yu-Lung LO Shu-Yu JIANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Vol. E87-A  No. 9  pp. 2210-2220
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
DLLPLLPORfast lockmultiphase outputs
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Circuit Analysis and Design of Low-Power CMOS Tapered Buffer
Kuo-Hsing CHENG Wei-Bin YANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/05/01
Vol. E86-C  No. 5  pp. 850-858
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
CMOS bufferinverted-delay-unitLPIDsplit-pathLBFSlow-swing bootstrappedcharge-transferfeedback-controlledsplit-pathCRFSpower-delay product
 Summary | Full Text:PDF