Kunio UCHIYAMA

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
Yoshitaka HIRAMATSU Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Toru NOJIRI Kunio UCHIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/12/01
Vol. E95-C  No. 12  pp. 1872-1882
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
block matching, heterogeneous multi-core, dynamically reconfigurable processor, data transfer, accelerator, 
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FOREWORD
Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 385-385
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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FOREWORD
Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 215-215
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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FOREWORD
Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10  pp. 1231-1231
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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FOREWORD
Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 519-520
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products
Naohiko IRIE Fumio ARAKAWA Kunio UCHIYAMA Shinichi YOSHIOKA Atsushi HASEGAWA Kevin IADONATE Mark DEBBAGE David SHEPHERD Margaret GEARTY 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 315-322
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
embedded processor, SIMD, preload, branch prediction, 
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A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications
Tetsuya YAMADA Makoto ISHIKAWA Yuji OGATA Takanobu TSUNODA Takahiro IRITA Saneaki TAMAKI Kunihiko NISHIYAMA Tatsuya KAMEI Ken TATEZAWA Fumio ARAKAWA Takuichiro NAKAZAWA Toshihiro HATTORI Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 253-262
Type of Manuscript:  INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
embedded processor, low power, RISC, DSP, MAC, 
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Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products
Kunio UCHIYAMA Fumio ARAKAWA Yasuhiko SAITO Koki NOGUCHI Atsushi HASEGAWA Shinichi YOSHIOKA Naohiko IRIE Takeshi KITAHARA Mark DEBBAGE Andy STURGES 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 139-149
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
embedded processor, RISC, SIMD, system-on-chip, multimedia, 
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Analog Circuit Design Methodology in a Low Power RISC Microprocessor
Koichiro ISHIBASHI Hisayuki HIGUCHI Toshinobu SHIMBO Kunio UCHIYAMA Kenji SHIOZAWA Naotaka HASHIMOTO Shuji IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A  No. 2  pp. 210-217
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
microprocessor, TLB, CAM, 0. 35 µm, CMOS, 
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Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH
Hideo MAEJIMA Masahiro KAINAGA Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1539-1545
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
RISC, architecture, low power, high speed, microprocessor, 
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