IEICE Trans

Kunihiro ASADA

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop Tetsuya IIZUKA Meikan CHIN Toru NAKURA Kunihiro ASADA
Publication: Publication Date: 2022/10/01 Vol. E105-C No. 10 pp. 544-551 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: clock-and-data recovery (CDR), time-to-digital converter (TDC), serial communication, quick start-up, internet-of-things,
	Summary \| Full Text:PDF

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction Masahiro KANO Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2018/04/01 Vol. E101-C No. 4 pp. 292-298 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: signal integrity, resonant power supply noise, triangular active charge injection, DLL, vernier TDC,
	Summary \| Full Text:PDF

Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting Toru NAKURA Tsukasa KAGAYA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2018/04/01 Vol. E101-C No. 4 pp. 218-223 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: quick start PLL, phase and frequency presetting,
	Summary \| Full Text:PDF

Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator Md. Maruf HOSSAIN Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA
Publication: Publication Date: 2018/02/01 Vol. E101-A No. 2 pp. 410-424 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: sub-ranging ADC, stochastic comparator, yield, probability density function, optimization, calibration,
	Summary \| Full Text:PDF

A PLL Compiler from Specification to GDSII Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2741-2749 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: PLL compiler, PLL synthesis, PWPLL, specification to GDSII,
	Summary \| Full Text:PDF

A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications Nguyen NGOC MAI-KHANH Kunihiro ASADA
Publication: Publication Date: 2017/12/01 Vol. E100-C No. 12 pp. 1078-1086 Type of Manuscript: PAPER Category: Microwaves, Millimeter-Waves Keyword: transceiver, broadband, CMOS, millimeter-wave, integrated circuit, pulse generator, antenna, active imaging,
	Summary \| Full Text:PDF

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring Tomohiko YANO Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2017/09/01 Vol. E100-C No. 9 pp. 736-745 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: time-mode circuit, analog front end, integrator, accumulator, time domain, calibration free,
	Summary \| Full Text:PDF

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR Parit KANJANAVIROJKUL Nguyen NGOC MAI-KHANH Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA
Publication: Publication Date: 2017/01/01 Vol. E100-A No. 1 pp. 200-209 Type of Manuscript: Special Section PAPER (Special Section on Wideband Systems) Category: Keyword: pulse generation, UWB-IR, CMOS, low duty cycle, energy efficiency, flip-chip devices,
	Summary \| Full Text:PDF

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing Masahiro ISHIDA Toru NAKURA Takashi KUSAKA Satoshi KOMATSU Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/10/01 Vol. E99-C No. 10 pp. 1219-1225 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: power integrity, power supply voltage control, overkills and underkills, delay fault testing, automatic test equipment,
	Summary \| Full Text:PDF

An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface Toshiyuki KIKKAWA Toru NAKURA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/02/01 Vol. E99-C No. 2 pp. 275-284 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: PLL, transfer function, lock range, on-chip measurement,
	Summary \| Full Text:PDF

Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer Toru NAKURA Masahiro KANO Masamitsu YOSHIZAWA Atsunori HATTORI Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-C No. 7 pp. 734-740 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: resonant power supply noise, power integrity, embedded capacitor, STO capacitor,
	Summary \| Full Text:PDF

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/08/01 Vol. E97-A No. 8 pp. 1688-1698 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: Electron Beam Direct Writing, Character Projection, routing, interconnect, VIA,
	Summary \| Full Text:PDF

A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters Satoshi KOMATSU Takahiro J. YAMAGUCHI Mohamed ABBAS Nguyen Ngoc MAI KHANH James TANDON Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/03/01 Vol. E97-A No. 3 pp. 777-780 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: flash TDC, arbiter, slope control,
	Summary \| Full Text:PDF

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2458-2466 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: electron beam direct writing, character projection, VIA, interconnect, routing,
	Summary \| Full Text:PDF

On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems Jinmyoung KIM Toru NAKURA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 560-567 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: DVS, fast voltage hopping, resonant supply noise, decoupling capacitor, noise reduction, capacitance boosting,
	Summary \| Full Text:PDF

Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 518-527 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: self synchronous, gate-level, robustness, single event upset, low voltage, reliability,
	Summary \| Full Text:PDF

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme Kazutoshi KODAMA Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/12/01 Vol. E95-C No. 12 pp. 1857-1863 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: DCO, ADPLL, high frequency resolution enhancement,
	Summary \| Full Text:PDF

All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction Sanad BUSHNAQ Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2234-2241 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: all-digital, sub-sampling, error correction,
	Summary \| Full Text:PDF

A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology Tetsuya IIZUKA Satoshi MIURA Ryota YAMAMOTO Yutaka CHIBA Shunichi KUBO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 661-667 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: time-to-digital converter, pulse shrinking, buffer ring,
	Summary \| Full Text:PDF

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 546-554 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: power gating, gate-level, pipeline, self synchronous, energy minimum operation, FPGA,
	Summary \| Full Text:PDF

All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator Tetsuya IIZUKA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 627-634 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: process variability, all digital, on-chip monitor, buffer ring,
	Summary \| Full Text:PDF

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 643-650 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: resonant supply noise, switched parasitic capacitors, sleep block, power gating,
	Summary \| Full Text:PDF

Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter Toru NAKURA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/02/01 Vol. E95-C No. 2 pp. 297-302 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: PLL, PWCO, pulse width control, soft thermometer code, LPF-less, quantization noise free,
	Summary \| Full Text:PDF

A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application Nguyen Ngoc MAI KHANH Masahiro SASAKI Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2554-2562 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: beam-forming, on-chip antenna array, integrated circuit, CMOS, jitter measurement, wide-band, millimeter-wave, active imaging,
	Summary \| Full Text:PDF

A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging Nguyen Ngoc MAI KHANH Masahiro SASAKI Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/10/01 Vol. E94-C No. 10 pp. 1626-1633 Type of Manuscript: Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology) Category: Microwave and Millimeter-Wave Antennas Keyword: pulse transmitter, loop antenna, millimeter-wave, integrated circuit, array antenna,
	Summary \| Full Text:PDF

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells Shingo MANDAI Tetsuya IIZUKA Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1098-1104 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: time-to-digital converter, TDC, time-difference-amplifier, TDA, time amp,
	Summary \| Full Text:PDF

Cascaded Time Difference Amplifier with Differential Logic Delay Cell Shingo MANDAI Toru NAKURA Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 654-662 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: time-difference-amplifier, TDA, time amp,
	Summary \| Full Text:PDF

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter Tetsuya IIZUKA Jaehyun JEONG Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 487-494 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: process variability, all digital, on-chip monitor, buffer ring, NBTI, PBTI,
	Summary \| Full Text:PDF

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 511-519 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: power supply noise, resonance, parasitic capacitance, sleep block, DVS, power gating,
	Summary \| Full Text:PDF

A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability Nguyen Ngoc MAI KHANH Masahiro SASAKI Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 627-634 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: shock wave, on-chip antenna, microwave, digitally programmable delay circuit, CMOS, beam-forming,
	Summary \| Full Text:PDF

Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method Shingo MANDAI Taihei MOMMA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/01/01 Vol. E94-C No. 1 pp. 124-127 Type of Manuscript: BRIEF PAPER Category: Microwaves, Millimeter-Waves Keyword: 3-D, address compression, image sensor, range-finder, light-section, row-parallel,
	Summary \| Full Text:PDF

A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform Salih ERGUN Ulkuhan GULER Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 pp. 180-190 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: random number generator, continuous-time chaotic oscillator, truly random,
	Summary \| Full Text:PDF

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment Benjamin STEFAN DEVLIN Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 pp. 1319-1328 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: self synchronous, fpga, pipeline alignment, low power, high throughput, dynamic logic, dual pipeline,
	Summary \| Full Text:PDF

Time Difference Amplifier with Robust Gain Using Closed-Loop Control Toru NAKURA Shingo MANDAI Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 303-308 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: time difference amplifier, TDA, time to digital converter, TDC, voltage controlled delay line,
	Summary \| Full Text:PDF

Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability Shingo MANDAI Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/06/01 Vol. E92-C No. 6 pp. 798-805 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: image sensor, light-section method, stereo-matching, dual imager core, multi functional range finder,
	Summary \| Full Text:PDF

A Structural Approach for Transistor Circuit Synthesis Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3529-3537 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: transistor-level synthesis, static CMOS circuits, algebraic transformations, structural transformations, dynamic programming,
	Summary \| Full Text:PDF

LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil Taisuke KAZAMA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3546-3550 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: character projection (CP), electron beam direct writing (EBDW), combined cell stencil (CCS), placement & routing,
	Summary \| Full Text:PDF

Autonomous di/dt Control of Power Supply for Margin Aware Operation Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1689-1694 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: autonomous di/dt control, margin aware, di/dt detector, power supply current,
	Summary \| Full Text:PDF

Noise Immunity Investigation of Low Power Design Schemes Mohamed ABBAS Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/08/01 Vol. E89-C No. 8 pp. 1238-1247 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: noise immunity, low power, power supply noise, digital design,
	Summary \| Full Text:PDF

On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function Mohamed ABBAS Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 370-376 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Signal Integrity and Variability Keyword: on-chip detector, non-periodic noise, high-swing noise,
	Summary \| Full Text:PDF

Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 364-369 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Signal Integrity and Variability Keyword: substrate noise, di/dt, feedforward active cancelling, anti-phase, ground bounce, di/dt detector,
	Summary \| Full Text:PDF

Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3485-3491 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: exact minimum-width transistor placement, Boolean Satisfiability, non-dual CMOS cells,
	Summary \| Full Text:PDF

Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/08/01 Vol. E88-C No. 8 pp. 1734-1739 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004) Category: Keyword: stub, on-board, power supply noise, di/dt noise, PRBS pattern,
	Summary \| Full Text:PDF

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/07/01 Vol. E88-A No. 7 pp. 1957-1963 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: comprehensive cell layout synthesis, CMOS logic cell, critical area, defect sensitivity, yield optimization,
	Summary \| Full Text:PDF

A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells Ulkuhan EKINCIEL Hiroaki YAMAOKA Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/06/01 Vol. E88-D No. 6 pp. 1159-1167 Type of Manuscript: PAPER Category: Computer Components Keyword: PLA, module generator, cell generation, HDL behavior generation,
	Summary \| Full Text:PDF

On-Chip di/dt Detector Circuit Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/05/01 Vol. E88-C No. 5 pp. 782-787 Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures) Category: Keyword: di/dt detector, mutual inductor, spiral inductor, parasitic inductance, power supply noise,
	Summary \| Full Text:PDF

Stub vs. Capacitor for Power Supply Noise Reduction Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/01/01 Vol. E88-C No. 1 pp. 125-132 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: stub, decoupling capacitor, power supply noise, di/dt noise, IR drop,
	Summary \| Full Text:PDF

Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition Yusuke OIKE Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/12/01 Vol. E87-C No. 12 pp. 2164-2171 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: image sensor, pixel-level color imaging, modulated RGB flashlight, object extraction, time-of-flight range finding, image recognition,
	Summary \| Full Text:PDF

High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3293-3300 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: high speed, cell layout synthesis, Boolean Satisfiability, SAT, CMOS logic cell, minimum width,
	Summary \| Full Text:PDF

Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories Yusuke OIKE Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1847-1855 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: associative memory, content addressable memory, CAM, Hamming distance, capacity scalability, multi-chip structure,
	Summary \| Full Text:PDF

A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits Hiroaki YAMAOKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/06/01 Vol. E87-C No. 6 pp. 1069-1077 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: PLA, high-speed, area-efficient, dual-rail,
	Summary \| Full Text:PDF

A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture Hiroaki YAMAOKA Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/02/01 Vol. E87-C No. 2 pp. 238-245 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: PLA, logic cell, dual-rail, array logic, area-efficient,
	Summary \| Full Text:PDF

A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method Yusuke OIKE Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/11/01 Vol. E86-C No. 11 pp. 2320-2328 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: position detector, smart image sensor, high speed, row-parallel architecture, 3-D camera,
	Summary \| Full Text:PDF

Design of a Conditional Sign Decision Booth Encoder for a High Performance 3232-Bit Digital Multiplier Minkyu SONG Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/09/01 Vol. E85-C No. 9 pp. 1709-1717 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: 3232-bit multiplier, conditional sign decision Booth encoder, compound logic, 9-2 compressor, 64-bit conditional select adder,
	Summary \| Full Text:PDF

High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit Yusuke OIKE Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/08/01 Vol. E85-C No. 8 pp. 1651-1658 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: position sensor, high sensitivity, wide dynamic range, logarithmic response, correlation,
	Summary \| Full Text:PDF

A System Level Optimization Technique for Application Specific Low Power Memories Tohru ISHIHARA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2755-2761 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: low power design, hardware/software codesign, memory, low voltage, embedded system,
	Summary \| Full Text:PDF

A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers Hiroaki YAMAOKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/09/01 Vol. E84-C No. 9 pp. 1240-1246 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: high speed, PLA, array logic circuit, sense amplifier,
	Summary \| Full Text:PDF

Functional Decomposition with Application to LUT-Based FPGA Synthesis Jian QIAO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/08/01 Vol. E84-A No. 8 pp. 2004-2013 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic synthesis, functional decomposition, compatibility class encoding, LUT-based FPGAs,
	Summary \| Full Text:PDF

Approaches for Reducing Power Consumption in VLSI Bus Circuits Kunihiro ASADA Makoto IKEDA Satoshi KOMATSU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/25 Vol. E83-C No. 2 pp. 153-160 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: low power, reduced signal swing, signal transition reduction, bus encoding/decoding, time-domain circuit, minimum Hamming-distance detector,
	Summary \| Full Text:PDF

Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI Tetsuhisa MIDO Hiroshi ITO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/04/25 Vol. E82-C No. 4 pp. 570-575 Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures) Category: Keyword: test structure, capacitance matrix, VLSI interconnection, shift registers, non-overlap clock signal, sub-femto-farad measurement,
	Summary \| Full Text:PDF

Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic Minkyu SONG Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/11/25 Vol. E81-C No. 11 pp. 1740-1749 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: power saved pass-transistor logic (PSPL), low power, regenerative feedback, 5454-bit multiplier, 7-bit serial counter,
	Summary \| Full Text:PDF

Power Optimization for Data Compressors Based on a Window Detector in a 5454 Bit Multiplier Minkyu SONG Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 1016-1024 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: a parallel structured architecture, low power data compressors, a Window Detector,
	Summary \| Full Text:PDF

An Image Scanning Method with Selective Activation of Tree Structure Junichi AKITA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 956-961 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multi Processors Keyword: image scan, tree structure, selective activation, automaton, image encoding,
	Summary \| Full Text:PDF

Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects Rimon IKENO Hiroshi ITO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/06/25 Vol. E80-C No. 6 pp. 806-811 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: SOI MOSFET, device simulation, subthreshold characteristics, quantum mechanical effects, parameter fitting, substrate bias,
	Summary \| Full Text:PDF

Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic Tsz-Shing CHEUNG Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/03/25 Vol. E80-C No. 3 pp. 478-488 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: pass-transistor logic, carry skip method, booth multiplier, monte carlo method.,
	Summary \| Full Text:PDF

A Synchronous Completion Prediction Adder (SCPA) Jeehan LEE Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 pp. 606-609 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: adder, CLA, completion prediction, completion detection,
	Summary \| Full Text:PDF

Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design Tsz Shing CHEUNG Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/09/25 Vol. E79-C No. 9 pp. 1274-1284 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: pass-transistor logic, dual-rail logic, Monte Carlo method, logic gates, arithmetic logic design,
	Summary \| Full Text:PDF

Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/03/25 Vol. E79-C No. 3 pp. 424-429 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: low power, partitioned-bus architecture, variable-width-bus scheme, microprocessor,
	Summary \| Full Text:PDF

Modeling of Leak Current Characteristics in High Frequency Operation of CMOS Circuits Fabricated on SOI Substrate Hiroshi ITO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/02/25 Vol. E79-C No. 2 pp. 185-191 Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures) Category: SOI & Material Characterization Keyword: leak current, threshold voltage shift, SOI, CMOS, inverter chain,
	Summary \| Full Text:PDF

Data Bypassing Register File for Low Power Microprocessor Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/10/25 Vol. E78-C No. 10 pp. 1470-1472 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: low power, data bypassing register file, microprocessor, implicit data bypassing scheme,
	Summary \| Full Text:PDF

A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability Kunihiro ASADA Junichi AKITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/25 Vol. E78-C No. 4 pp. 436-440 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: DA/Architecture Keyword: charge and discharge power, probability parameter, finite state machine, signal assignment, output probability,
	Summary \| Full Text:PDF

Ultimate Lower Bound of Power for MOS Integrated Circuits and Their Applications Kunihiro ASADA Mike LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/25 Vol. E77-C No. 7 pp. 1131-1137 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SOI, deep submicron, charging and discharging energy, recycled energy, TDGC model, transient device simulation, finite element method, future MOS LSI,
	Summary \| Full Text:PDF

Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM) Kyoung-Rok CHO Kazuma OKURA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/04/25 Vol. E77-C No. 4 pp. 615-623 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: completion signal, asynchronous microprocessor, self-timed data path, DCVSL,
	Summary \| Full Text:PDF

FOREWORD Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/02/25 Vol. E77-C No. 2 pp. 91-91 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator Yasukazu IWASAKI Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/02/25 Vol. E77-A No. 2 pp. 371-379 Type of Manuscript: Special Section PAPER (Special Section on High-Performance MOS Analog Circuits) Category: Keyword: simulation, power-NOSFET, avalanche, cylinder, heat generation,
	Summary \| Full Text:PDF

A Proposal of High Speed and Low Power Data Transmission Method for VLSIs by Reduced-Swing Signal Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 pp. 1666-1675 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword:
	Summary \| Full Text:PDF

A New Proposal for Inverter Delay Improvement on CMOS/SOI Future Technology M.O. LEE Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/10/25 Vol. E76-C No. 10 pp. 1515-1522 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: TPD time-dependent gate capacitance(TDGC), SOI, deep sub-micrometer, CMOS, poly-si gate thickness(t_m), ring oscillator,
	Summary \| Full Text:PDF

Analytical Modeling of Dynamic Performance of Deep Sub-micron SOI/SIMOX Based on Current-Delay Product Minoru FUJISHIMA Makoto IKEDA Kunihiro ASADA Yasuhisa OMURA Katsutoshi IZUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/12/25 Vol. E75-C No. 12 pp. 1506-1514 Type of Manuscript: Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices) Category: Deep Sub-micron SOI CMOS Keyword: CMOS, SOI, deep-submicron, modeling, ring oscillator,
	Summary \| Full Text:PDF

Thickness Uniformity Improvement of YBa₂Cu₃O_y (6y7) Films by Metal Organic Chemical Vapor Deposition with a Tapered Inner Tube Masayuki SUGIURA Yasuhiko MATSUNAGA Kunihiro ASADA Takuo SUGANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/08/25 Vol. E75-C No. 8 pp. 911-917 Type of Manuscript: Special Section PAPER (Special Issue on Cryogenic Microwave Devices) Category: Passive Devices Keyword: oxide superconductor, film, tapered inner tube, metal organic chemical vapor deposition, YBaCuO,
	Summary \| Full Text:PDF

1/5 Power Law in PN-Junction Failure Mechanism Caused by Electrical-Over-Stress Yutaka TAJIMA Kunihiro ASADA Takuo SUGANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/02/25 Vol. E75-C No. 2 pp. 207-215 Type of Manuscript: Special Section PAPER (Special Issue on Selected Papers from '91 VPAD) Category: Keyword: reliability, failure, pn-junction, silicon, electrostatic-discharge,
	Summary \| Full Text:PDF

FOREWORD Tokuo SUGANO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/01/25 Vol. E74-C No. 1 pp. 117-118 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

A Design Method of Pseudo-Self-Checking LSI System Using Cascode Voltage Switch Logic Kunio NAKAGURO Kunihiro ASADA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/12/25 Vol. E73-E No. 12 pp. 1973-1978 Type of Manuscript: Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Keyword:
	Summary \| Full Text:PDF

Automatic Deconvolution in DLTS Signals Analysis Kunihiro ASADA Takuo SUGANO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1982/12/25 Vol. E65-E No. 12 pp. 745-749 Type of Manuscript: PAPER Category: Semiconductors Keyword:
	Summary \| Full Text:PDF