Kumpei YOSHIKAWA

AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model
Kumpei YOSHIKAWA Kouji ICHIKAWA Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4  pp. 264-271
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
power supply noise, electromagnetic compatibility, LSI chip-package-board co-design, power integrity, 
 Summary | Full Text:PDF
Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits
Takeshi OKUMOTO Kumpei YOSHIKAWA Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 538-545
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
noise detection circuit, power supply noise, power supply integrity, systems-on-a-chip, 
 Summary | Full Text:PDF
Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
Kumpei YOSHIKAWA Yuta SASAKI Kouji ICHIKAWA Yoshiyuki SAITO Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2284-2291
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
LSI chip-package-board co-design, electromagnetic compatibility, power supply noise, power delivery network, 
 Summary | Full Text:PDF
Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation
Takuya SAWADA Taku TOSHIKAWA Kumpei YOSHIKAWA Hidehiro TAKATA Koji NII Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 586-593
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
SRAM, Immunity, On chip monitoring, Built-in self testing, 
 Summary | Full Text:PDF