Kozo KINOSHITA


SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines
Jun YAMASHITA Hiroyuki YOTSUYANAGI Masaki HASHIZUME Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2561-2567
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
open faultsadjacent linestest pattern generationcoupling capacitanceSAT-based ATPG
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A Novel ATPG Method for Capture Power Reduction during Scan Testing
Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Tatsuya SUZUKI Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/09/01
Vol. E90-D  No. 9  pp. 1398-1405
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
scan testingcapture powerX-bitIR-drop
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A Per-Test Fault Diagnosis Method Based on the X-Fault Model
Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/11/01
Vol. E89-D  No. 11  pp. 2756-2765
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
fault diagnosisper-testX-fault model
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A New Method for Low-Capture-Power Test Generation for Scan Testing
Xiaoqing WEN Yoshiyuki YAMASHITA Seiji KAJIHARA Laung-Terng WANG Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/05/01
Vol. E89-D  No. 5  pp. 1679-1686
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
scan testingcapture powerX-bitIR-drop
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On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies
Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/04/01
Vol. E88-D  No. 4  pp. 703-710
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
fault diagnosisIDDQtransistor leakage fault modelmultiple power supplycircuit partitioning
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Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits
Kazuya SHIMIZU Takanori SHIRAI Masaya TAKAMURA Noriyoshi ITAZAKI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1526-1533
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
domino circuitcrosstalk faulttarget fault reductionfault simulation
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IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates
Masaki HASHIZUME Teppei TAKEDA Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Yukiya MIURA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1534-1541
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Current Test
Keyword: 
IDDQ sensorCMOSIDDQ testbridging fault
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Analysis of IDDQ Occurrence in Testing
Arabi KESHK Yukiya MIURA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/04/01
Vol. E84-D  No. 4  pp. 534-536
Type of Manuscript:  LETTER
Category: Computer System Element
Keyword: 
IDDQ testingbridging faultfault analysis
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On Processing Order for Obtaining Implication Relations in Static Learning
Hideyuki ICHIHARA Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10  pp. 1908-1911
Type of Manuscript:  LETTER
Category: Fault Tolerance
Keyword: 
test generationimplicationstatic learning
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Power Estimation and Reduction of CMOS Circuits Considering Gate Delay
Hiroaki UEDA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/01/25
Vol. E82-D  No. 1  pp. 301-308
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
CMOS circuitlow power designgate delaytransition probabilityswitching activity
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Test Generation for Sequential Circuits under IDDQ Testing
Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 689-696
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
sequential circuittest generationIDDQ testingbridging fault
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Logic Optimization: Redundancy Addition and Removal Using Implication Relations
Hideyuki ICHIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 724-730
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Logic Simulation and Logic Optimization
Keyword: 
logic optimizationimplicationredundancy identification
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Transistor Leakage Fault Diagnosis for CMOS Circuits
Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 697-705
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
fault diagnosistransistor leakage faultIDDQprimary outputfault simulationdiagnostic test generation
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Transistor Leakage Fault Diagnosis with IDDQ and Logic Information
Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/04/25
Vol. E81-D  No. 4  pp. 372-381
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault diagnosistransistor leakage faultIDDQ testingfault simulationdiagnostic vector generation
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A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits
Noriyoshi ITAZAKI Yasutaka IDOMOTO Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1  pp. 38-43
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Testing/Checking
Keyword: 
crosstalk faultfault simulationsequential circuittest
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Testing of k-FR Circuits under Highly Observable Condition
Xiaoqing WEN Hideo TAMAMOTO Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 830-838
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
testable designfault testinghighly observable conditioncircuit conversion
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Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
Seiji KAJIHARA Rikiya NISHIGAYA Tetsuji SUMIOKA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 811-816
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generationmultiple stuck-at faultvector pair analysiscombinational circuit
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Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement
Hiroyuki YOTSUYANAGI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 861-867
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
retiminglogic synthesisredundancy removaltest synthesis
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Efficient Guided-Probe Fault Location Method for Sequential Circuits
Xiaoging WEN Kozo KINOSHITA Hideo TAMAMOTO Hiroshi YOKOYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/02/25
Vol. E78-D  No. 2  pp. 122-129
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
guided-probe fault locationselection of lines to probesequential circuitVLSI diagnosis
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A Reduced Scan Shift Method for Sequential Circuit Testing
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2010-2016
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
sequential circuittest generationdesign for testabilityscan circuitreduced scan shift
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Throughput Analysis of ARQ Schemes in Dialogue Communication over Half-Duplex Line
Chun-Xiang CHEN Masaharu KOMATSU Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/04/25
Vol. E77-B  No. 4  pp. 485-493
Type of Manuscript:  PAPER
Category: Communication Theory
Keyword: 
throughputARQ schemehalf-duplex linedialogue communication
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Traffic Analysis of the Stop-and-Wait ARQ over A Markov Error Channel
Masaharu KOMATSU Chun-Xiang CHEN Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/04/25
Vol. E77-B  No. 4  pp. 477-484
Type of Manuscript:  PAPER
Category: Communication Theory
Keyword: 
queueing analysisstop-and-wait ARQdependent error
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Channel-Grouping Methods on Go-Back-N ARQ Scheme in Multiple-Parallel-Channel System
Chun-Xiang CHEN Masaharu KOMATSU Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/02/25
Vol. E77-B  No. 2  pp. 265-269
Type of Manuscript:  LETTER
Category: Communication Theory
Keyword: 
channel-grouping methodsthroughputARQ schememultiple-channel system
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Throughput Performances of ARQ Protocols Operating over Generalized Two-State Markov Error Channel
Masaharu KOMATSU Yukuo HAYASHIDA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/01/25
Vol. E77-B  No. 1  pp. 35-42
Type of Manuscript:  PAPER
Category: Communication Theory
Keyword: 
throughputARQ protocolMarkov error channeldependent error
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Consecutive Customer Loss Phenomenon due to Buffer Overflow in Finite Buffer Queueing System
Masaharu KOMATSU Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1781-1789
Type of Manuscript:  PAPER
Category: Queueing Theory
Keyword: 
modeling and simulationwueueing theory
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Test Sequence Generation for Sequential Circuits with Distinguishing Sequences
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1730-1737
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
distinguishing sequencestuck-at faultsequential circuittest sequence generationdesign rechnique
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Synthesis of Testable Sequential Circuits with Reduced Checking Sequences
Satoshi SHIBATANI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 739-746
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
sequential circuitdesign for testabilityautomated logic synthesischecking sequencestate assignment
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FOREWORD
Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 737-738
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF

Efficient Methods for Guided-Probe Diagnosis
WEN Xiaoqing Noriyoshi ITAZAKI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 817-825
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
guided-probe diagnosisE-beam probingprobing line determination methodfault probability
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Performance Evaluation of Block SR-ARQ Scheme in High-Speed Communication Environments
Chunxiang CHEN Masaharu KOMATSU Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1992/12/25
Vol. E75-B  No. 12  pp. 1338-1345
Type of Manuscript:  Special Section PAPER (Special Issue on Teletraffic)
Category: 
Keyword: 
block SR-ARQ schemehigh-speed communication environmentsthroughputpacket delay
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A Testable Design of Sequential Circuits under Highly Observable Condition
WEN Xiaoqing Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/05/25
Vol. E75-D  No. 3  pp. 334-341
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
design for testabilityhighly observable testingfault diagnosissequential circuitcircuit modification
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Testable Design for Stuck-Open Faults with the Robustness
Yukiya MIURA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/08/25
Vol. E73-E  No. 8  pp. 1294-1300
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Systems)
Category: 
Keyword: 
 Summary | Full Text:PDF

FOREWORD
Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/08/25
Vol. E73-E  No. 8  pp. 1245-1246
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF