Koyo NITTA


Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture
Ken NAKAMURA Daisuke KOBAYASHI Yuya OMORI Tatsuya OSAWA Takayuki ONISHI Koyo NITTA Hiroe IWASAKI 
Publication:   
Publication Date: 2020/03/01
Vol. E103-C  No. 3  pp. 77-84
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
HEVCdecoderhigh frame ratetemporal scalability
 Summary | Full Text:PDF(2.8MB)

Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
Yuta UKON Koji YAMAZAKI Koyo NITTA 
Publication:   
Publication Date: 2020/01/01
Vol. E103-B  No. 1  pp. 11-19
Type of Manuscript:  Special Section PAPER (Special Section on Internet Architecture, Applications and Operation Technologies for a Cyber-Physical System)
Category: Network System
Keyword: 
service function chainingreal-time image processingpacket-reordering circuitCPU-FPGA architecture
 Summary | Full Text:PDF(2.3MB)

An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures
Koyo NITTA Hiroe IWASAKI Takayuki ONISHI Takashi SANO Atsushi SAGATA Yasuyuki NAKAJIMA Minoru INAMORI Ryuichi TANIDA Atsushi SHIMIZU Ken NAKAMURA Mitsuo IKEDA Jiro NAGANUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 432-440
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
H.264/AVCencoderMPSoCME/MCand HDTV
 Summary | Full Text:PDF(4.1MB)

Motion Estimation and Compensation Hardware Architecture for a Scene-Adaptive Algorithm on a Single-Chip MPEG-2 Video Encoder
Koyo NITTA Toshihiro MINAMI Toshio KONDO Takeshi OGURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/03/01
Vol. E84-D  No. 3  pp. 317-325
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
motion estimation and compensationscene-adaptive algorithmMPEG-2 video encoderhardware architectureSIMD
 Summary | Full Text:PDF(4.3MB)

Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI
Mitsuo IKEDA Toshio KONDO Koyo NITTA Kazuhito SUGURI Takeshi YOSHITOME Toshihiro MINAMI Jiro NAGANUMA Takeshi OGURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 170-178
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
MPEG-2video signal processingembedded system LSIhardware/software co-designpicture coding
 Summary | Full Text:PDF(2.5MB)

Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses
Kazuyoshi TAKAGI Koyo NITTA Hironori BOUNO Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/04/25
Vol. E80-A  No. 4  pp. 663-669
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computational complexityBoolean functionordered binary decision diagramsatisfiabilitycombinational circuitcutwidthsum-of-product formzero-suppressed binary decision diagrams (BDD)ternary decision diagram
 Summary | Full Text:PDF(675.4KB)