Kotaro TERADA

A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines
Daisuke OKU Kotaro TERADA Masato HAYASHI Masanao YAMAOKA Shu TANAKA Nozomu TOGAWA 
Publication:   
Publication Date: 2019/09/01
Vol. E102-D  No. 9  pp. 1696-1706
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
CMOS annealing, Ising model, Ising computing, graph embedding, combinatorial optimization, 
 Summary | Full Text:PDF
A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures
Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2911-2924
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesis, multiple-bitwidth, distributed-register architecture, operation chaining, interconnection delay, floorplan, 
 Summary | Full Text:PDF
A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures
Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1366-1375
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesis, RDR architecture, interconnection delay, operation chaining, floorplan, 
 Summary | Full Text:PDF