Koji YAMAZAKI

Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
Yuta UKON Koji YAMAZAKI Koyo NITTA 
Publication:   
Publication Date: 2020/01/01
Vol. E103-B  No. 1  pp. 11-19
Type of Manuscript:  Special Section PAPER (Special Section on Internet Architecture, Applications and Operation Technologies for a Cyber-Physical System)
Category: Network System
Keyword: 
service function chaining, real-time image processing, packet-reordering circuit, CPU-FPGA architecture, 
 Summary | Full Text:PDF(2.3MB)
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
Koji YAMAZAKI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 661-666
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
fault diagnosis, open fault, BIST, pass/fail information, 
 Summary | Full Text:PDF(570.7KB)
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 675-682
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
diagnosis, fault model, fault location, fault simulation, combinational circuits, pass/fail information, 
 Summary | Full Text:PDF(491.4KB)
Post-BIST Fault Diagnosis for Multiple Faults
Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 771-775
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category: 
Keyword: 
post-BIST fault diagnosis, multiple stuck-at faults, combinational circuits, pass/fail information, 
 Summary | Full Text:PDF(88.5KB)
A Single Bridging Fault Location Technique for CMOS Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 817-821
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
fault diagnosis, bridging fault, CMOS, combinational circuit, 
 Summary | Full Text:PDF(398KB)
SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 826-831
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fault diagnosis, gate-level fault, combinational circuit, probing, 
 Summary | Full Text:PDF(455.2KB)