Publication: Publication Date: 2019/04/01 Vol. E102-CNo. 4pp. 287-295 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: nonvolatile memory, magnetic memory, memory architecture,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-CNo. 4pp. 332-341 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: design for robustness, cache, variation tolerance, 7T/14T SRAM,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-ANo. 12pp. 2695-2702 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Memory Design and Test Keyword: 6T SRAM cell, 8T SRAM cell, Vth variation,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-CNo. 10pp. 1949-1956 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Next-Generation Memory for SoC Keyword: 6T SRAM cell, 8T SRAM cell, Vth variation,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-ANo. 12pp. 3634-3641 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: SRAM, DVS, Vth-variation-tolerant, low power,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-CNo. 4pp. 563-570 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: low power, high speed, microcontroller, SOI,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/03/01 Vol. E86-CNo. 3pp. 439-446 Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02)) Category: Keyword: embedded SRAM, scaling merit, 3-dimensional interconnect simulation, 50 and 70 nm technology nodes,