IEICE Trans

Koji NAKAJIMA

CMOS Majority Circuit with Large Fan-In Hisanao AKIMA Yasuhiro KATAYAMA Masao SAKURABA Koji NAKAJIMA Jordi MADRENAS Shigeo SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/09/01 Vol. E99-C No. 9 pp. 1056-1064 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: majority logic, MOS analog circuits, nonlinear circuits, Monte Carlo simulation,
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FOREWORD Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 pp. 131-131 Type of Manuscript: FOREWORD Category: Keyword:
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Neuron Circuit Using Coupled SQUIDs Gate with Flat Output Characteristics for Superconducting Neural Network Takeshi ONOMI Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 pp. 173-177 Type of Manuscript: Special Section PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits) Category: Keyword: superconducting circuit, SQUID, neural network, combinatorial optimization problem,
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High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform Ryosuke NAKAMOTO Sakae SAKURABA Alexandre MARTINS Takeshi ONOMI Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/03/01 Vol. E94-C No. 3 pp. 280-287 Type of Manuscript: Special Section PAPER (Special Section on Superconducting Signal Processing Technologies) Category: Keyword: SFQ, super-conductive circuits, FFT, multiplier, adder,
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Recalling Temporal Sequences of Patterns Using Neurons with Hysteretic Property Johan SVEHOLM Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 943-950 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: temporal sequences of patterns, limit inverse function delayed neuron, negative resistance,
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Hardware Neural Network for a Visual Inspection System Seungwoo CHUN Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 935-942 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: hardware, visual inspection system, back-propagation, PCI-BUS, FPGA,
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Avoidance of the Permanent Oscillating State in the Inverse Function Delayed Neural Network Akari SATO Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/10/01 Vol. E90-A No. 10 pp. 2101-2107 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Neuron and Neural Networks Keyword: neural network, combinatorial optimization problem, N-Queen problem, inverse function delayed model, negative resistance,
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Design of a Neural Network Chip for the Burst ID Model with Ability of Burst Firing Shinya SUENAGA Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 715-723 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: burst firing, neural network, optimization problem, LSI,
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Macroscopic Quantum Tunneling and Resonant Activation of Current Biased Intrinsic Josephson Junctions in Bi-2212 Shigeo SATO Kunihiro INOMATA Mitsunaga KINJO Nobuhiro KITABATAKE Koji NAKAJIMA Huabing WANG Takeshi HATANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/03/01 Vol. E90-C No. 3 pp. 599-604 Type of Manuscript: INVITED PAPER (Special Section on Innovative Superconducting Devices and Their Applications) Category: Keyword: Josephson junction, macroscopic quantum tunneling, high-Tc superconductor, resonant activation, qubit,
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Dynamical Behavior of Neural Networks with Anti-Symmetrical Cyclic Connections Shinya SUENAGA Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/10/01 Vol. E89-A No. 10 pp. 2775-2786 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Oscillation, Dynamics and Chaos Keyword: neural network, limit cycles,
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Temporal Sequences of Patterns with an Inverse Function Delayed Neural Network Johan SVEHOLM Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/10/01 Vol. E89-A No. 10 pp. 2818-2824 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Control, Neural Networks and Learning Keyword: temporal sequences of patterns, inverse function delayed model, negative resistance,
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Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic Hongge LI Yoshihiro HAYAKAWA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/09/01 Vol. E89-D No. 9 pp. 2572-2578 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: inverse function delayed model, associative memory, field programmable gate array (FPGA), stochastic logic,
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Retrieval Property of Associative Memory Based on Inverse Function Delayed Neural Networks Hongge LI Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/08/01 Vol. E88-A No. 8 pp. 2192-2199 Type of Manuscript: PAPER Category: Nonlinear Problems Keyword: associative memory, inverse function delayed model, retrieval dynamics, basin of attraction, negative resistance,
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Single Electron Stochastic Neural Network Hisanao AKIMA Saiboku YAMADA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/09/01 Vol. E87-A No. 9 pp. 2221-2226 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: single electron transistor (SET), artificial neural network (ANN), stochastic logic, single electron random number generator,
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Implementation of Continuous-Time Dynamics on Stochastic Neurochip Shunsuke AKIMOTO Akiyoshi MOMOI Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/09/01 Vol. E87-A No. 9 pp. 2227-2232 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: stochastic logic, nonmonotonic neuron, continuous-time dynamics, asynchronous updating, associative memories, traveling salesman problem, large scale integration (LSI) implementation,
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Asymptotic Analysis of Cyclic Transitions in the Discrete-Time Neural Networks with Antisymmetric and Circular Interconnection Weights Cheol-Young PARK Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/06/01 Vol. E87-A No. 6 pp. 1487-1490 Type of Manuscript: Special Section LETTER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003)) Category: Keyword: discrete-time neural networks, cyclic transitions, circular interconnection weights, limit cycle,
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Single Electron Random Number Generator Hisanao AKIMA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/05/01 Vol. E87-C No. 5 pp. 832-834 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: random number generator, single electron transistor, Monte Carlo simulation,
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Comparison between an AND Array and a Booth Encoder for Large-Scale Phase-Mode Multipliers Yohei HORIMA Itsuhei SHIMIZU Masayuki KOBORI Takeshi ONOMI Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/01/01 Vol. E86-C No. 1 pp. 16-23 Type of Manuscript: Special Section PAPER (Special Issue on Superconductor Digital/Analog Circuit Technologies) Category: LTS Digital Application Keyword: single flux quantum, Phase-Mode parallel multiplier, hybrid structure, AND array, Booth encoder,
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FOREWORD Koji NAKAJIMA Masaki SANO Yoshinori HAYAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/09/01 Vol. E85-A No. 9 pp. 1987-1987 Type of Manuscript: FOREWORD Category: Keyword:
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Hardware Implementation of a DBM Network with Non-monotonic Neurons Mitsunaga KINJO Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/03/01 Vol. E85-D No. 3 pp. 558-567 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: neural network, non-monotonic, DBM learning, analog circuit, neurochip,
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Majority Algorithm: A Formation for Neural Networks with the Quantized Connection Weights Cheol-Young PARK Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/25 Vol. E83-A No. 6 pp. 1059-1065 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99)) Category: Keyword: neural networks, multi-layer, limit cycles, quantized interconnection, parity problem,
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Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles Cheol-Young PARK Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/06/25 Vol. E82-A No. 6 pp. 952-957 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98)) Category: Keyword: neural network, limit cycles, quantized interconnection, programmable synapse, pattern classifier,
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A Content-Addressable Memory Using "Switched Diffusion Analog Memory with Feedback Circuit" Tomochika HARADA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 370-377 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: nonvolatile analog memory, content-addressable memory, recognition, SDAM, analog technology,
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Integrated Circuits of Map Chaos Generators Hidetoshi TANAKA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 364-369 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: chaotic noise, map chaos, integrated circuit, Lyapunov exponent, neural network,
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Phase-Mode Circuits for High-Performance Logic Takeshi ONOMI Yoshinao MIZUGAKI Hideki SATOH Tsutomu YAMASHITA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/10/25 Vol. E81-C No. 10 pp. 1608-1617 Type of Manuscript: INVITED PAPER (Special Issue on Low- and High-Temperature Superconductive Electron Devices and Their Applications) Category: Digital Applications Keyword: superconductive electronics, Josephson junction, single flux quantum, logic circuit, integrated circuit,
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Binary Counter with New Interface Circuits in the Extended Phase-Mode Logic Family Takeshi ONOMI Yoshinao MIZUGAKI TsutomuYAMASHITA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/09/25 Vol. E79-C No. 9 pp. 1200-1205 Type of Manuscript: Special Section PAPER (Special Issue on Toward Digital and Analog Applications of Superconductors) Category: Superconductive digital integrated circuits Keyword: superconductive electronics, single flux quantum, logic circuit, Josephson junction, binary counter,
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Limit Cycles of One-Dimensional Neural Networks with the Cyclic Connection Matrix Cheol-Young PARK Yoshihiro HAYAKAWA Koji NAKAJIMA Yasuji SAWADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/06/25 Vol. E79-A No. 6 pp. 752-757 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1995 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '95)) Category: Keyword: neural networks, continuous-time model, dynamics, limit cycles, equilibrium point,
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Switched Diffusion Analog Memory for Neural Networks with Hebbian Learning Function and Its Linear Operation Hyosig WON Yoshihiro HAYAKAWA Koji NAKAJIMA Yasuji SAWADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/06/25 Vol. E79-A No. 6 pp. 746-751 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1995 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '95)) Category: Keyword: floating-gate analog memory, three cascaded TFTs, learning chip, source follower operation of TFT, accurate linearity,
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Neuro-Base Josephson Flip-Flop Yoshinao MIZUGAKI Koji NAKAJIMA Tsutomu YAMASHITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/05/25 Vol. E78-C No. 5 pp. 531-534 Type of Manuscript: Special Section PAPER (Special Issue on Superconducting Electronics and Its Applications) Category: Superconducting integrated circuits Keyword: superconductive electronics, dc-biased Josephson flip-flop, coupled-SQUIDs, neural network, high-J_c,
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LSI Neural Chip of Pulse-Output Network with Programmable Synapse Shigeo SATO Manabu YUMINE Takayuki YAMA Junichi MUROTA Koji NAKAJIMA Yasuji SAWADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/01/25 Vol. E78-C No. 1 pp. 94-100 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: neurochip, pulse, analog, programmable synapse,
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Hardware Implementation of New Analog Memory for Neural Networks Koji NAKAJIMA Shigeo SATO Tomoyasu KITAURA Junichi MUROTA Yasuji SAWADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/01/25 Vol. E78-C No. 1 pp. 101-105 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: analog memory, floating gate, neurochip, SDAM,
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Linearization Analysis of Threshold Characteristics for Some Applications of Mutually Coupled SQUIDs Yoshinao MIZUGAKI Koji NAKAJIMA Tsutomu YAMASHITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/08/25 Vol. E76-C No. 8 pp. 1291-1297 Type of Manuscript: Special Section PAPER (Special Issue on High-Temperature Superconducting Electronics) Category: Keyword: superconductive electronics, mutually coupled SQUIDs, linearization, logic gate, neuron device, A/D converter,
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