Koichi NISHIMURA


Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface
Yoshinori OKAJIMA Masao TAGUCHI Miki YANAGAWA Koichi NISHIMURA Osamu HAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 798-807
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
DLLsynchronous interfaceDRAMbus timing skew
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