Kohji KANAMORI


Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
Hiroshi SUGAWARA Toshio TAKESHIMA Hiroshi TAKADA Yoshiaki S. HISAMUNE Kohji KANAMORI Takeshi OKAZAWA Tatsunori MUROTANI Isao SASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 825-831
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memory64 Mbitmulti-bit programmingdata registerhierarchical
 Summary | Full Text:PDF

A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories
Kohji KANAMORI Yosiaki S. HISAMUNE Taishi KUBOTA Yoshiyuki SUZUKI Masaru TSUKIJI Eiji HASEGAWA Akihiko ISHITANI Takeshi OKAZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1296-1302
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: Non-volatile Memory
Keyword: 
F-N tunnelingflash memoryoxynitridelow power supply
 Summary | Full Text:PDF