IEICE Trans

Kiyoo ITOH

0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell Khaja Ahmad SHAIK Kiyoo ITOH Amara AMARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/02/01 Vol. E99-A No. 2 pp. 523-530 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: 0.5-V 5T-cell SRAM array, multi-divided open bit-lines, boosted word-line, mid-point sensing,
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0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs Akira KOTABE Kiyoo ITOH Riichiro TAKEMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 555-563 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: 0.5-V 25-nm 6-T SRAM cell, boosted word voltage, FD-MOSFETs, repair, worst design,
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A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing Satoru AKIYAMA Riichiro TAKEMURA Tomonori SEKIGUCHI Akira KOTABE Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 600-608 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: low-voltage DRAM, gated preamplifier, mid-point sensing, variations in threshold voltage,
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Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays Akira KOTABE Riichiro TAKEMURA Yoshimitsu YANAGAWA Tomonori SEKIGUCHI Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 594-599 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: DRAM, low voltage, sense amplifier, mid-point sensing,
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Adaptive Circuits for the 0.5-V Nanoscale CMOS Era Kiyoo ITOH Masanao YAMAOKA Takashi OSHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 216-233 Type of Manuscript: INVITED PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: minimum operating voltage, SRAM, DRAM, FD-SOI, FinFET,
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Long-Retention-Time, High-Speed DRAM Array with 12-F² Twin Cell for Sub 1-V Operation Riichiro TAKEMURA Kiyoo ITOH Tomonori SEKIGUCHI Satoru AKIYAMA Satoru HANZAWA Kazuhiko KAJIGAYA Takayuki KAWAHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 758-764 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: twin-cell DRAM array, write time, low voltage RAM, retention time, and plate-driven cell,
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Low-Voltage and Low-Power ULSI Circuit Techniques Masakazu AOKI Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 pp. 1351-1360 Type of Manuscript: INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: General Technology Keyword: battery operation, subthreshold current, switched power-line scheme, self-reverse biasing, switched source impedance, hierarchical power line, partial activation of circuit blocks, charge recycle, reference-voltage generator,
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The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips Takao WATANABE Masakazu AOKI Katsutaka KIMURA Takeshi SAKATA Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1206-1214 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Neural Networks and Chips Keyword: DRAM-based neuro-chip, 10⁶-synapse neural network, 1.5-V digital chip, 0.5-µm CMOS design rule,
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Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's Yoshinobu NAKAGOME Kiyoo ITOH Masanori ISODA Kan TAKEUCHI Masakazu AOKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/05/25 Vol. E76-C No. 5 pp. 754-759 Type of Manuscript: Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993)) Category: Keyword:
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Stabilization of Voltage Limiter Circuit for High-Density DRAM's Using Pole-Zero Compensation Hitoshi TANAKA Masakazu AOKI Jun ETOH Masashi HORIGUCHI Kiyoo ITOH Kazuhiko KAJIGAYA Tetsurou MATSUMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/11/25 Vol. E75-C No. 11 pp. 1333-1343 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Keyword: memory, DRAM, voltage limiter, pole-zero compensation,
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Deep-Submicrometer BiCMOS Circuit Technology for Sub-10-ns ECL 4-Mb DRAM's Takayuki KAWAHARA Yoshiki KAWAJIRI Goro KITSUKAWA Kazuhiko SAGARA Yoshifumi KAWAMOTO Takesada AKIBA Shisei KATO Yasushi KAWASE Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/25 Vol. E75-C No. 4 pp. 487-494 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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Reviews and Prospects of DRAM Technology Yoshinobu NAKAGOME Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/25 Vol. E74-C No. 4 pp. 799-811 Type of Manuscript: INVITED PAPER (Special Issue on LSI Memories) Category: DRAM Keyword:
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VLSI Memories: Present Status and Future Prospects Toshiaki MASUHARA Kiyoo ITOH Koichi SEKI Katsuro SASAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/01/25 Vol. E74-C No. 1 pp. 130-141 Type of Manuscript: INVITED PAPER Category: Keyword:
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