IEICE Trans

Kimiyoshi USAMI

Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM Yoshinori ONO Kimiyoshi USAMI
Publication: Publication Date: 2021/07/01 Vol. E104-C No. 7 pp. 338-349 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: non-volatile memory, magnetic tunnel junction, write energy, approximate computing, image data, image quality,
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Energy-Efficient Standard Cell Memory with Optimized Body-Bias Separation in Silicon-on-Thin-BOX (SOTB) Yusuke YOSHIDA Kimiyoshi USAMI
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2785-2796 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: standard cell memory, silicon-on-thin-box (SOTB), energy-efficient, ultra-low voltage, body bias,
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Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems Akram BEN AHMED Hiroki MATSUTANI Michihiro KOIBUCHI Kimiyoshi USAMI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 pp. 909-917 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: Network-on-Chips, multi-Vdd, low power networks,
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An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications Atsushi KOSHIBA Mikiko SATO Kimiyoshi USAMI Hideharu AMANO Ryuichi SAKAMOTO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 pp. 926-935 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: energy conservation, power gating, operating system, microprocessor,
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A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units Atsushi KOSHIBA Motoki WADA Ryuichi SAKAMOTO Mikiko SATO Tsubasa KOSAKA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-C No. 7 pp. 559-568 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: energy conservation, power gating, operating system, Linux,
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An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1376-1391 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, energy-optimization, interconnection delay, multiple clock domains,
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A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode Koichiro ISHIBASHI Nobuyuki SUGII Shiro KAMOHARA Kimiyoshi USAMI Hideharu AMANO Kazutoshi KOBAYASHI Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-C No. 7 pp. 536-543 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: microprocessor, low power design,
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FOREWORD Kimiyoshi USAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2457-2457 Type of Manuscript: FOREWORD Category: Keyword:
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Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2597-2611 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, interconnection delay, energy-optimization, dynamic multiple supply voltages,
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Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design Hiroshi NAKAMURA Weihan WANG Yuya OHTA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 404-412 Type of Manuscript: INVITED PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: low-power circuit techniques, fine grained power-gating, compiler, system hierarchy cooperation,
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Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model Seidai TAKEDA Kyundong KIM Hiroshi NAKAMURA Kimiyoshi USAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2499-2509 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power gating, MTCMOS, delay, leakage power,
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Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits Naoaki OHKUBO Kimiyoshi USAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3482-3490 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: MTCMOS, selective-MT, static timing analysis, leakage power, delay modeling,
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Dynamic Sleep Control for Finite-State-Machines to Reduce Active Leakage Power Kimiyoshi USAMI Hiroshi YOSHIOKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3116-3123 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: leakage power, scaling, active leakage, burn-in, MTCMOS,
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Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications Kimiyoshi USAMI Naoyuki KAWABE Masayuki KOIZUMI Katsuhiro SETA Toshiyuki FURUSAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2667-2673 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: high performance, low standby leakage, multi-threshold, MTCMOS, W-CDMA,
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