| Kimihiro YAMAKOSHI
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A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz Hiroki SUTOH Kimihiro YAMAKOSHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C
No. 7
pp. 1334-1340
Type of Manuscript:
PAPER Category: Integrated Electronics Keyword: PLL, CMOS/SIMOX, VCO, clock, jitter, skew, lock range, | | Summary | Full Text:PDF(2MB) | |
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