IEICE Trans

Kewal K. SALUJA

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line Yoshinobu HIGAMI Senling WANG Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA
Publication: Publication Date: 2017/09/01 Vol. E100-D No. 9 pp. 2224-2227 Type of Manuscript: LETTER Category: Dependable Computing Keyword: fault diagnosis, bridging faults, clock lines,
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Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/06/01 Vol. E96-D No. 6 pp. 1323-1331 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test generation, fault simulation, clock line, delay fault,
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A Study of Capture-Safe Test Generation Flow for At-Speed Testing Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 pp. 1309-1318 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: at-speed scan testing, test generation, X-bit identification, X-filling, capture-safety checking,
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Addressing Defect Coverage through Generating Test Vectors for Transistor Defects Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3128-3135 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: test generation, transistor defects, stuck-at tests, defect coverage,
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Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3506-3513 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: fault simulation, test generation, stuck-open faults, stuck-at tests, defect coverage,
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Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 690-699 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Defect-Based Testing Keyword: transistor short, fault simulation, test generation, stuck-at test tool,
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A Novel ATPG Method for Capture Power Reduction during Scan Testing Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Tatsuya SUZUKI Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/09/01 Vol. E90-D No. 9 pp. 1398-1405 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop,
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Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability Masato NAKAZATO Satoshi OHTAKE Kewal K. SALUJA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 pp. 296-305 Type of Manuscript: PAPER Category: Dependable Computing Keyword: sequential circuit, test generation, synthesis for testability, finite state machine, test knowledge,
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A Per-Test Fault Diagnosis Method Based on the X-Fault Model Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2756-2765 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, per-test, X-fault model,
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A New Method for Low-Capture-Power Test Generation for Scan Testing Xiaoqing WEN Yoshiyuki YAMASHITA Seiji KAJIHARA Laung-Terng WANG Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/05/01 Vol. E89-D No. 5 pp. 1679-1686 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop,
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Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1165-1172 Type of Manuscript: PAPER Category: Dependable Computing Keyword: BIST, fault diagnosis, error identification, at-speed test, low speed tester,
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On Design for I_DDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/04/01 Vol. E88-D No. 4 pp. 703-710 Type of Manuscript: PAPER Category: Computer Components Keyword: fault diagnosis, I_DDQ, transistor leakage fault model, multiple power supply, circuit partitioning,
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An Alternative Test Generation for Path Delay Faults by Using N_i-Detection Test Sets Hiroshi TAKAHASHI Kewal K. SALUJA Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2650-2658 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Test Keyword: test generation, path delay faults N-propagation test-pair set, combinational circuits,
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Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1515-1525 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test and Diagnosis for Timing Faults Keyword: diagnosis, crosstalk fault, fault simulation, sequential circuit,
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Transistor Leakage Fault Diagnosis for CMOS Circuits Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 697-705 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Fault Diagnosis Keyword: fault diagnosis, transistor leakage fault, I_DDQ, primary output, fault simulation, diagnostic test generation,
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Transistor Leakage Fault Diagnosis with I_DDQ and Logic Information Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/04/25 Vol. E81-D No. 4 pp. 372-381 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: fault diagnosis, transistor leakage fault, I_DDQ testing, fault simulation, diagnostic vector generation,
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Theory and Techniques for Testing Check Bits of RAMs with On-Chip ECC Manoj FRANKLIN Kewal K. SALUJA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/10/25 Vol. E76-D No. 10 pp. 1243-1252 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: error-correcting codes, on-chip ECC, pattern sensitive faults, RAM testing, test algorithms,
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