Kentaro YOSHIOKA


An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS
Ryota SEKIMOTO Akira SHIKATA Kentaro YOSHIOKA Tadahiro KURODA Hiroki ISHIKURO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Vol. E96-C  No. 6  pp. 820-827
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
ADCSARultra low powerasynchronous
 Summary | Full Text:PDF

A 4–10 bit, 0.4–1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller
Akira SHIKATA Ryota SEKIMOTO Kentaro YOSHIOKA Tadahiro KURODA Hiroki ISHIKURO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/02/01
Vol. E96-A  No. 2  pp. 443-452
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog-to-digital convertersuccessive approximationasynchronousdifferential flip-flop
 Summary | Full Text:PDF