Kentaro KAWAKAMI

Accelerating LiNGAM Causal Discovery with Massive Parallel Execution on Supercomputer Fugaku
Kazuhito MATSUDA Kouji KURIHARA Kentaro KAWAKAMI Masafumi YAMAZAKI Fuyuka YAMADA Tsuguchika TABARU Ken YOKOYAMA 
Publication:   
Publication Date: 2022/12/01
Vol. E105-D  No. 12  pp. 2032-2039
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
Fugaku, performance tuning, causal discovery, LiNGAM, 
 Summary | Full Text:PDF
A Binary Translator to Accelerate Development of Deep Learning Processing Library for AArch64 CPU
Kentaro KAWAKAMI Kouji KURIHARA Masafumi YAMAZAKI Takumi HONDA Naoto FUKUMOTO 
Publication:   
Publication Date: 2022/06/01
Vol. E105-C  No. 6  pp. 222-231
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
deep learning, oneDNN, AArch64, just-in-time assembler, binary translator, 
 Summary | Full Text:PDF
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline
Kentaro KAWAKAMI Jun TAKEMURA Mitsuhiko KURODA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3642-3651
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
H.264/AVC, DVS (dynamic voltage scaling), elastic pipeline, low power, divided entropy decoder, 
 Summary | Full Text:PDF
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond
Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3634-3641
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
SRAM, DVS, Vth-variation-tolerant, low power, 
 Summary | Full Text:PDF
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era
Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Jun TAKEMURA Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3290-3297
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
low power, dynamic voltage frequency scaling (DVFS), adaptive body biasing, Vdd-hopping, Vth-hopping, 
 Summary | Full Text:PDF
A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU
Hideo OHIRA Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 457-465
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
MPEG4 encoder, low power, feed-forward voltage control, multi-regulated voltage CPU, 
 Summary | Full Text:PDF