Kenta YAMADA

Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
Kenta YAMADA Toshiyuki SYO Hisao YOSHIMURA Masaru ITO Tatsuya KUNIKIYO Toshiki KANAMOTO Shigetaka KUMASHIRO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1349-1358
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
STI, stress, model, verification, enhancement, 
 Summary | Full Text:PDF
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
Kenta YAMADA Takashi SATO Shuhei AMAKAWA Noriaki NAKAYAMA Kazuya MASU Shigetaka KUMASHIRO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/07/01
Vol. E91-C  No. 7  pp. 1142-1150
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
STI, stress, modeling, SPICE, layout-aware, 
 Summary | Full Text:PDF
Accurate Modeling Method for Cu Interconnect
Kenta YAMADA Hiroshi KITAHARA Yoshihiko ASAI Hideo SAKAMOTO Norio OKADA Makoto YASUDA Noriaki ODA Michio SAKURAI Masayuki HIROI Toshiyuki TAKEWAKI Sadayuki OHNISHI Manabu IGUCHI Hiroyasu MINDA Mieko SUZUKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C  No. 6  pp. 968-977
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
Cu, interconnect, cross-section, modeling, 
 Summary | Full Text:PDF
Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)
Kenta YAMADA Noriaki ODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 562-570
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
statistical, corner conditions, interconnect, LPE, delay, 
 Summary | Full Text:PDF
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation
Noriaki ODA Hironori IMURA Naoyoshi KAWAHARA Masayoshi TAGAMI Hiroyuki KUNISHIMA Shuji SONE Sadayuki OHNISHI Kenta YAMADA Yumi KAKUHARA Makoto SEKINE Yoshihiro HAYASHI Kazuyoshi UENO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 848-855
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Device
Keyword: 
copper, low-k, CMOS, interconnect, design, application, 
 Summary | Full Text:PDF