Kenji SHIOZAWA

A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
Kenichi OSADA Hisayuki HIGUCHI Koichiro ISHIBASHI Naotaka HASHIMOTO Kenji SHIOZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/01/25
Vol. E83-C  No. 1  pp. 109-114
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
cache, SRAM, low power, two-port, microprocessor, 
 Summary | Full Text:PDF
Analog Circuit Design Methodology in a Low Power RISC Microprocessor
Koichiro ISHIBASHI Hisayuki HIGUCHI Toshinobu SHIMBO Kunio UCHIYAMA Kenji SHIOZAWA Naotaka HASHIMOTO Shuji IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A  No. 2  pp. 210-217
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
microprocessor, TLB, CAM, 0. 35 µm, CMOS, 
 Summary | Full Text:PDF
Development and Fabrication of Digital Neural Network WSIs
Minoru FUJITA Yasushi KOBAYASHI Kenji SHIOZAWA Takahiko TAKAHASHI Fumio MIZUNO Hajime HAYAKAWA Makoto KATO Shigeki MORI Tetsuro KASE Minoru YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1182-1190
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
neural network, WSI, CMOS, electron-beam direct-writing, 
 Summary | Full Text:PDF