Kenji OGURA

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core
Tetsuya YAMADA Masahide ABE Yusuke NITTA Kenji OGURA Manabu KUSAOKE Makoto ISHIKAWA Motokazu OZAWA Kiwamu TAKADA Fumio ARAKAWA Osamu NISHII Toshihiro HATTORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 287-294
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Low Power Techniques
Keyword: 
embedded processor, clock, gated clock, flip-flop, 
 Summary | Full Text:PDF
A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor
Toshihiro HATTORI Kenji OGURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 520-526
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
threshold voltage, low power, dual-Vth, physical synthesis, 
 Summary | Full Text:PDF