Kenji NODA

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
Kohei MIYASE Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Yuta YAMATO Hiroshi FURUKAWA Xiaoqing WEN Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/06/01
Vol. E94-D  No. 6  pp. 1216-1226
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
ATPG, X-bit, X-identification, X-filling, 
 Summary | Full Text:PDF
A Study of Capture-Safe Test Generation Flow for At-Speed Testing
Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7  pp. 1309-1318
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
at-speed scan testing, test generation, X-bit identification, X-filling, capture-safety checking, 
 Summary | Full Text:PDF
High-Level Synthesis for Weakly Testable Data Paths
Michiko INOUE Kenji NODA Takeshi HIGASHIMURA Toshimitsu MASUZAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 645-653
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Test Synthesis
Keyword: 
high-level synthesis, testability, sequential ATPG, non-scan design, 
 Summary | Full Text:PDF
Design Rule Relaxation Approach for High-Density DRAMs
Takanori SAEKI Eiichiro KAKEHASHI Hidemitu MORI Hiroki KOGA Kenji NODA Mamoru FUJITA Hiroshi SUGAWARA Kyoichi NAGATA Shozo NISHIMOTO Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3  pp. 406-415
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
DRAM, design rule, close packed cell array, Boosted Dual Word-Line scheme, 
 Summary | Full Text:PDF
Availability Analysis on Two-Unit Parallel Redundant System When Failure is Detected Only by Inspection
Kouichi ADACHI Masanori KODAMA Kenji NODA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1980/01/25
Vol. E63-E  No. 1  pp. 43-44
Type of Manuscript:  LETTER
Category: Electromagnetic Theory, Mathematics, Pyhsics
Keyword: 
 Summary | Full Text:PDF