Kenji ANAMI


Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
Hideyuki NODA Kazunari INOUE Hans Jurgen MATTAUSCH Tetsushi KOIDE Katsumi DOSAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Kenji ANAMI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 622-629
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
CMOSTernary CAMnetworkrefresh
 Summary | Full Text:PDF

A Study of Delay Time on Bit Lines in Megabit SRAM's
Atsushi KINOSHITA Shuji MURAKAMI Yasumasa NISHIMURA Kenji ANAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11  pp. 1383-1386
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
SRAMcoupling capacitancebit-line
 Summary | Full Text:PDF

A New Soft-Error Phenomenon is ULSI SRAM's--Inverted Dependence of Soft-Error Rate on Cycle Time--
Shuji MURAKAMI Tomohisa WADA Masanao EINO Motomu UKITA Yasumasa NISHIMURA Kimio SUZUKI Kenji ANAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 853-858
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: SRAM
Keyword: 
 Summary | Full Text:PDF

A Study on Fanout Optimization of SRAM Decoder with a Line Capacitance
Shigeki OHBAYASHI Tomohisa WADA Toshihiko HIROSE Kenji ANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1855-1857
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF

A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's
Hirotoshi SATO Shuji MURAKAMI Yasumasa NISHIMURA Toshihiko HIROSE Kenji ANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1858-1860
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF

An Analysis of Substrate Current in Memory Cell for ULSI SRAM
Yoshiyuki HARAGUCHI Shuji MURAKAMI Yasumasa NISHIMURA Kenji ANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1861-1862
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF