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A Study on Fanout Optimization of SRAM Decoder with a Line Capacitance
Shigeki OHBAYASHI Tomohisa WADA Toshihiko HIROSE Kenji ANAMI | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E
No. 11
pp. 1855-1857
Type of Manuscript:
Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword:
| | | Summary | Full Text:PDF | |
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A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's
Hirotoshi SATO Shuji MURAKAMI Yasumasa NISHIMURA Toshihiko HIROSE Kenji ANAMI | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E
No. 11
pp. 1858-1860
Type of Manuscript:
Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword:
| | | Summary | Full Text:PDF | |
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An Analysis of Substrate Current in Memory Cell for ULSI SRAM
Yoshiyuki HARAGUCHI Shuji MURAKAMI Yasumasa NISHIMURA Kenji ANAMI | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E
No. 11
pp. 1861-1862
Type of Manuscript:
Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword:
| | | Summary | Full Text:PDF | |
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