Kenichi NAKASHI

A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD
Hiroyasu YOSHIZAWA Kenji TANIGUCHI Hiroyuki SHIRAHAMA Kenichi NAKASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6  pp. 1015-1020
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
PLL, PFD, VCO, low power, source coupling, dynamic circuit, 
 Summary | Full Text:PDF
Computer Simulation of Jitter Characteristics of PLL for Arbitrary Data and Jitter Patterns
Kenichi NAKASHI Hiroyuki SHIRAHAMA Kenji TANIGUCHI Osamu TSUKAHARA Tohru EZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6  pp. 977-984
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Analog Circuits and Signal Processing
Keyword: 
PLL, jitter, time-domain simulation, phase detector, NRZ, retiming, 
 Summary | Full Text:PDF