IEICE Trans

Keishi SAKANUSHI

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring Hirofumi IWATO Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 487-494 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: pressure sensing, urinary bladder, SoC, low power, ASIP,
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Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design Ittetsu TANIGUCHI Ayataka KOBAYASHI Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2659-2668 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: forward error correction (FEC), decoder model,
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Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor Takuji HIEDA Hiroaki TANAKA Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3258-3267 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: partial forwarding, instruction scheduling, compiler, design space exploration,
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Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems Hassan A. YOUNESS Keishi SAKANUSHI Yoshinori TAKEUCHI Ashraf SALEM Abdel-Moneim WAHDAN Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1088-1095 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: optimal scheduling, task graphs, state-space search, A^*, geometric analysis,
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Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram Hiroaki TANAKA Yoshinori TAKEUCHI Keishi SAKANUSHI Masaharu IMAI Hiroki TAGAWA Yutaka OTA Nobu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2800-2809 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: compiler, SIMD instructions, multi-valued decision diagram,
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EQ-Sequences for Coding Floorplans Hua-An ZHAO Chen LIU Yoji KAJITANI Keishi SAKANUSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3233-3243 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Floorplan Keyword: floorplan, placement, VLSI CAD, Q-sequence,
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An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair Kazuya WAKATA Hiroaki SAITO Kunihiro FUJIYOSHI Keishi SAKANUSHI Takayuki OBATA Chikaaki KODAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3148-3157 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Place and Routing Keyword: packing, sequence-pair, convex rectilinear block,
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Recognition of Floorplan by Parametric BSG for Reuse of Layout Design Keishi SAKANUSHI Zhonglin WU Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 872-879 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: parametric BSG, layout, reuse, floorplan, technology migration,
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The 3D-Packing by Meta Data Structure and Packing Heuristics Hiroyuki YAMAZAKI Keishi SAKANUSHI Shigetoshi NAKATAKE Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/04/25 Vol. E83-A No. 4 pp. 639-645 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: 3D-packing, placement, sequence-pair, sequence-triple, simulated annealing,
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