IEICE Trans

Keikichi TAMARU

Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2400-2408 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: VLSI, functional memory, DRAM, parallel processor, block matching,
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Layout Dependent Matching Analysis of CMOS Circuits Kenichi OKADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 348-355 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: CMOS, matching, micro-loading-effect, fluctuation,
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A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization Kazutoshi KOBAYASHI Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 215-222 Type of Manuscript: Special Section PAPER (Special Section on VLSI for Digital Signal Processing) Category: Keyword: vector quantization, functional memory, parallel processor, low-rate image compression, noise robustness, MSHVQ,
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A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits Masanori HASHIMOTO Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/01/25 Vol. E82-A No. 1 pp. 159-166 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: input reordering, transistor reordering, power estimation,
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CAM-Based Array Converter for URR Floating-Point Arithmetic Kuei-Ming LU Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/10/25 Vol. E81-D No. 10 pp. 1120-1130 Type of Manuscript: PAPER Category: Computer Applications Keyword: floating-point arithmetic, content addressable memory, iterative array, URR format conversion,
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An LSI for Low Bit-Rate Image Compression Using Vector Quantization Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 pp. 718-724 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: parallel processor, memory-based, vector quantization, low bit-rate image compression, low power, SIMD,
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Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/25 Vol. E81-A No. 3 pp. 462-469 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: short-circuit power dissipation, short-circuit current, resistive-capacitive load, CRC π load, output waveform, gate delay,
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A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ Kazutoshi KOBAYASHI Masayoshi KINOSHITA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 970-975 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multi Processors Keyword: parallel processor, memory-base, vector quantization, low bit-rate image compression, SIMD,
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A Current Mode Cyclic A/D Converter with Submicron Processes Masaki KONDO Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/02/25 Vol. E80-A No. 2 pp. 360-364 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques for System-on-Chip Integration) Category: Keyword: A/D, A/D converter, current mode, ratio-independent, RGC,
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A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs Vasily G. MOSHNYAGA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/25 Vol. E79-D No. 10 pp. 1389-1395 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Synthesis Keyword: high-level synthesis, ASIC design methodology,
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Estimation of short-Circuit Power Dissipation for Static CMOS Gates Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 pp. 304-311 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: short-circuit power dissipation, short-circit current, simulation of power dissipation, low power disign, power estimation,
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Model-Adaptable Parameter Extraction System for MOSFET Models Masaki KONDO Takashi MORIE Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/05/25 Vol. E78-A No. 5 pp. 569-572 Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Fall Conference) Category: Keyword: parameter extraction system, initial value estimation, MOSFET characterization,
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Register-Transfer Module Selection for Sub-Micron ASIC Design Vasily G. MOSHNYAGA Yutaka MORI Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-D No. 3 pp. 252-255 Type of Manuscript: Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design) Category: Keyword: module selection, register-transfer synthesis,
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Development of Module Generators from Extracted Design Procedures--Application to Analog Device Generation-- Takashi MORIE Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/02/25 Vol. E78-A No. 2 pp. 160-168 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Computer Aided Design) Category: Keyword: device layout, module generation, analog LSI, store and re-use, design procedure,
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Experiments with Power Optimization in Gate Sizing Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/11/25 Vol. E77-A No. 11 pp. 1913-1916 Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference) Category: Keyword: low power design, power dissipation, gate sizing, area–power–delay tradeoff,
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The Trend of Functional Memory Development Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 pp. 1545-1554 Type of Manuscript: INVITED PAPER (Special Issue on LSI Memories) Category: Keyword: memory, functional memory, content addressable memory, associative memory, processor array,
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Design of a Multiplier-Accumulator for High Speed lmage Filtering Farhad Fuad ISLAM Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/11/25 Vol. E76-A No. 11 pp. 2022-2032 Type of Manuscript: PAPER Category: VLSI Design Technology Keyword: binary multiplier-accumulator, throughput, image filtering, VLSI architecture,
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A Language for Designing Module Generators Vasily G. MOSHNYAGA Keikichi TAMARU Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 pp. 1066-1074 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Hardware Design Languages Keyword: module generator, hardware disign language,
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An Architecture for High Speed Array Multiplier Farhad Fuad ISLAM Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/08/25 Vol. E76-A No. 8 pp. 1326-1333 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: binary multiplication, array multipler, VLSI architecture,
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Hardware Architecture for Kohonen Network Hidetoshi ONODERA Kiyoshi TAKESHITA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1159-1166 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Neural Networks and Chips Keyword: neural network, Kohonen network, massively parallel computation, content addressable memory,
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A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture Kazutoshi KOBAYASHI Keikichi TAMARU Hiroto YASUURA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1151-1158 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Memory-Based Parallel Processor Architectures Keyword: parallel processor, memory-based simple structure, logical and arithmetic operations,
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FOREWORD Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/11/25 Vol. E75-C No. 11 pp. 1303-1303 Type of Manuscript: FOREWORD Category: Keyword:
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Extraction of Behavioral Descriptions from Synchronous Sequential Circuits Masahiko OHMURA Hiroto YASUURA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 pp. 1239-1246 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: behavioral extraction, logic verification,
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An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique Farhad Fuad ISLAM Hiroto YASUURA Keikichi TAMARU
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/11/25 Vol. E73-E No. 11 pp. 1810-1812 Type of Manuscript: Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE) Category: Signals, Circuits and Images Keyword:
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Module Generation of a CMOS Op Amp Using a Non-linear Optimization Method Hidetoshi ONODERA Hiroyuki KANBARA Keikichi TAMARU
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1988/10/25 Vol. E71-E No. 10 pp. 947-949 Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1988 Autumn Convention IEICE) Category: Integrated Circuit Keyword:
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